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X-CSE-ConnectionGUID: OweoqK9lSKa5n0CF7wNypQ== X-CSE-MsgGUID: t0/XKnF9T8u3kKlq10A/PA== X-IronPort-AV: E=McAfee;i="6600,9927,11065"; a="33297039" X-IronPort-AV: E=Sophos;i="6.07,259,1708416000"; d="scan'208";a="33297039" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 13:28:24 -0700 X-CSE-ConnectionGUID: DjyiNd3sSXCtcE/QcWH6wQ== X-CSE-MsgGUID: qLl6V1eMSCOnYYGhS3ERIQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,259,1708416000"; d="scan'208";a="28242490" Received: from djiang5-mobl3.amr.corp.intel.com (HELO [10.124.222.135]) ([10.124.222.135]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2024 13:28:22 -0700 Message-ID: <3d18ae36-4dea-496a-a8fc-253b21135838@intel.com> Date: Mon, 6 May 2024 13:28:21 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [LSF/MM/BPF TOPIC] CXL Development Discussions To: Adam Manzanares , "lsf-pc@lists.linux-foundation.org" , "dan.j.williams@intel.com" , "jonathan.cameron@huawei.com" , "dave@stgolabs.net" , Fan Ni , "ira.weiny@intel.com" , "alison.schofield@intel.com" , "vishal.l.verma@intel.com" , "gourry.memverge@gmail.com" , "wj28.lee@gmail.com" , "rientjes@google.com" , "ruansy.fnst@fujitsu.com" , "shradha.t@samsung.com" , "mcgrof@kernel.org" , Jim Harris , "mhocko@suse.com" Cc: "linux-mm@kvack.org" , "linux-cxl@vger.kernel.org" , "linux-pci@vger.kernel.org" References: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> Content-Language: en-US From: Dave Jiang In-Reply-To: <9bf86b97-319f-4f58-b658-1fe3ed0b1993@nmtadam.samsung> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Rspamd-Queue-Id: 4FACB100010 X-Rspam-User: X-Rspamd-Server: rspam03 X-Stat-Signature: 1zzjpssctrmkpnc6a4kp5xaoouubwc9a X-HE-Tag: 1715027304-691852 X-HE-Meta: U2FsdGVkX1911qxSFyVpvnwlIWe8HsmeyWECs1U/Tz97ZYgGLoD9oMBKP8+kyGRQrT/USiCIrJm6UK/abKqVGQxgpUI3FqmrqMmx61uTMY4Vgvtq//Tr+A3QIdqP5OZxPNj9YoMku7f44yq3wp+8Yp6FseEP2/0CGcNF2T+kEAPvR25qWJmmjQFzdHh0SO81Gmv/az/QLfmXXewupqfPvXDrbiL7ukiyMkItS64UC6JqwT+5kBI0dFYj8TcP/GHjPKzeVVYfZisb6ciq2hzjCMVwj/szqd4XeJ+7uSuEy3mzSXuJ3rK7AbYf8VbMHXOpI5EkafuhnExns5Ma9W8zN/tkDzNmQ8BzTkwdo5KHGG2PEfxByqdEvZXs0qJfmphfrPcfVmIcktHkG/uNeu9mpkrScriawZR74biVM1s4v1WqcR9FH/nudUm1wFqpIfYuq7TeRxu8iLYXH/y9rhmjL8BnsrkbFt2ALLmWHa+59ZGTp4Pumjte+PlC5EHwN9JtSaxvUQ2PNjSUhMeF8pZoQdfrMcCuy4bBL3/W2Xaa8VibyRNKoHJynpIGeu0Pyp2NMCVjXcBEhoCvVWYAyBCQxFJ3byBf2jf2kvfAcZAFHjIGAXYnRjoueHiUrcKg50WHJ/DvRQIkEEnkXMBqGBQjK11jAqNpO4evtxI7aaDLaaTEg8SqO6mflm2bD81afFGIPX6wdpWSHZAmlto4K+9IxZsK5GZORlvtyOlL3cWyWcAQk4ZWy0SCFzhPWiqQnCBGtAuaMoXgG0u2rxLc3JSWSOUhszz1Kp5jDHxdu2Rx1Tt8ts1e/oBSw7RNxynqSjR2kBzE7skjhWp/suh2g72w/IrmRqVazO5xCGr6t7iJAqX5dMDr6c58TX5Ye2Wn7OSIJMbok1n3LogCMq3mHFl0r+CI1R+Xfvqjt0IBWzEn7A8QwEsvKnoeAxadaZWTdiC4Nm3MaFH/4S+TsIf67D2 qLndGaZs 5qLC9XjbQYGiB04wt6bfTpXllAEHtrZcd+uLDhomdVYIMBaIsKQNnRj5Xc5j6quJk6P+L/at1aRo5468uaRAALQX2aFV2EiqjXByZk1aOj+geBR1kVXIZCHYfqh/xJfeGY3Mou9SUEvDPbIrGSxjuPzzk2Tou2cFFsMHy5r/R1EGGRglg3oCXRIFRbkQMTXqAo3DDilPfuIw/JpYmcfIFCNkR366+/jg85V0nQt8MoNKvRifslmXEcJGHF3wRfiuk+4t0ulW9Gxl15MVfhL0a8jwl54XwaXVuIUKCGApWXyiz2N2QzioWM2dmcsNqDtzbVrbdp1wOXhzE7ghGizv6YkJfWTx6fipM7txAmvBu78TwGuML5KqSfl+H4zpYiORvBTFAAEjDB1E8ZwRksqYqrfACpSTk9U6DLMRyi/8slchpcV0= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 5/6/24 12:27 PM, Adam Manzanares wrote: > Hello all, > > I would like to have a discussion with the CXL development community about > current outstanding issues and also invite developers interested in RAS and > memory tiering to participate. > > The first topic I believe we should discuss is how we can ensure as a group > that we are prioritizing upstream work. On a recent upstream CXL development > discussion call there was a call to review more work. I apologize for not > grabbing the link, but I believe Dave Jiang is leveraging patchwork and this > link should be shared with others so we can help get more reviews where needed. Bundle for the potential fixes https://patchwork.kernel.org/bundle/cxllinux/cxl-fixes/ Bundle for the next merge window https://patchwork.kernel.org/bundle/cxllinux/cxl-next/ Just be aware patchwork only takes patches, so the bundle are registered with the first patch of a series. The listing does display the origin series. DJ > > The second topic I would like to discuss is how we integrate RAS features that > have similar equivalents in the kernel. A CXL device can provide info about > memory media errors in a similar fashion to memory controllers that have EDAC > support. Discussions have been put on the list and I would like to hear thoughts > from the community about where this should go [1]. On the same topic CXL has > port level RAS features and the PCIe DW series touched on this issue [2] > > The third topic I would like to discuss is how we can get a set of common > benchmarks for memory tiering evaluations. Our team has done some initial > work in this space, but we want to hear more from end users about their > workloads of concern. There was a proposal related to this topic, but from what > I understand no meeting has been held [3]. > > The last topic that I believe is worth discussion is how do we come up with > a baseline for testing. I am aware of 3 efforts that could be used cxl_test, > qemu, and uunit testing framework [4]. > > Apologies for getting this out late, and please include anyone that may be > interested in joining a discussion. > > [1] https://lore.kernel.org/linux-cxl/20240417075053.3273543-1-ruansy.fnst@fujitsu.com/ > [2] https://lore.kernel.org/lkml/20231130115044.53512-1-shradha.t@samsung.com/ > [3] https://lore.kernel.org/all/2b29dd3d-bb2c-6a8c-94d2-d5c2e035516a@google.com > [4] https://lore.kernel.org/linux-cxl/170795677066.3697776.12587812713093908173.stgit@ubuntu/