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[209.85.220.65]) by mx.google.com with SMTPS id g3sor15718175plp.57.2019.02.11.11.18.57 for (Google Transport Security); Mon, 11 Feb 2019 11:18:57 -0800 (PST) Received-SPF: pass (google.com: domain of nadav.amit@gmail.com designates 209.85.220.65 as permitted sender) client-ip=209.85.220.65; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=TvVF7Po4; spf=pass (google.com: domain of nadav.amit@gmail.com designates 209.85.220.65 as permitted sender) smtp.mailfrom=nadav.amit@gmail.com; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=U6QTzJmyKky3utGjaHrGeaTnG1UolmYGOzcU+sH5Y+4=; b=TvVF7Po4LRk8+UgMyGoXm30CgOd2P6lLmVQn5RZpI5wUzIIoXXtfNAIuqOawTWBGPz fS8pjD5cnntQXdELvDLrmIhIFRbp16FQ9xPi/oZa9wRP2NsSsk0ZeyiZlhdJ7Q6TWS9p B/lWPUJG7L51x8P3v11HCJuoAlMo5Cxh6bqt53b7xu5PEh2sbNjmF4hY8sZSsijX50TG z9qwZ9yHnDkkM/UvCy1vFaOs16f61CnxVKCy2cLC/H939Gke2R+uKpDmLiFm/rkL5Wmt ULnZbBqh7G3JPu66P9osymbRJoRcdI/lfk173jGzpMMFkFolagtGay4aT+8Gc3jvSfLT izzA== X-Google-Smtp-Source: AHgI3IanC/OTNWPI8Kzdg7h23REmR+aXWc9nczhB8ikk5z0mmrBH5R/gEZhhv/eMlxu6ih5oZqdkJQ== X-Received: by 2002:a17:902:32c3:: with SMTP id z61mr38926435plb.114.1549912737334; Mon, 11 Feb 2019 11:18:57 -0800 (PST) Received: from [10.33.115.182] ([66.170.99.1]) by smtp.gmail.com with ESMTPSA id z7sm14168103pga.6.2019.02.11.11.18.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Feb 2019 11:18:56 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 12.2 \(3445.102.3\)) Subject: Re: [PATCH v2 05/20] x86/alternative: initializing temporary mm for patching From: Nadav Amit In-Reply-To: Date: Mon, 11 Feb 2019 11:18:54 -0800 Cc: Rick Edgecombe , Ingo Molnar , LKML , X86 ML , "H. Peter Anvin" , Thomas Gleixner , Borislav Petkov , Dave Hansen , Peter Zijlstra , Damian Tometzki , linux-integrity , LSM List , Andrew Morton , Kernel Hardening , Linux-MM , Will Deacon , Ard Biesheuvel , Kristen Carlson Accardi , "Dock, Deneen T" , Kees Cook , Dave Hansen Content-Transfer-Encoding: quoted-printable Message-Id: <3EA322C6-5645-4900-AEC6-97FC05716F75@gmail.com> References: <20190129003422.9328-1-rick.p.edgecombe@intel.com> <20190129003422.9328-6-rick.p.edgecombe@intel.com> <162C6C29-CD81-46FE-9A54-6ED05A93A9CB@gmail.com> <00649AE8-69C0-4CD2-A916-B8C8F0F5DAC3@amacapital.net> <6FE10C97-25FF-4E99-A96A-465CBACA935B@gmail.com> To: Andy Lutomirski X-Mailer: Apple Mail (2.3445.102.3) X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: > On Feb 11, 2019, at 11:07 AM, Andy Lutomirski wrote: >=20 > I'm certainly amenable to other solutions, but this one does seem the > least messy. I looked at my old patch, and it doesn't do what you > want. I'd suggest you just add a percpu variable like cpu_dr7 and rig > up some accessors so that it stays up to date. Then you can skip the > dr7 writes if there are no watchpoints set. >=20 > Also, EFI is probably a less interesting example than rare_write. > With rare_write, especially the dynamically allocated variants that > people keep coming up with, we'll need a swath of address space fully > as large as the vmalloc area. and getting *that* right while still > using the kernel address range might be more of a mess than we really > want to deal with. As long as you feel comfortable with this solution, I=E2=80=99m fine = with it. Here is what I have (untested). I prefer to save/restore all the DRs, because IIRC DR6 indications are updated even if breakpoints are = disabled (in DR7). And anyhow, that is the standard interface. -- >8 -- From: Nadav Amit Date: Mon, 11 Feb 2019 03:07:08 -0800 Subject: [PATCH] mm: save DRs when loading temporary mm Signed-off-by: Nadav Amit --- arch/x86/include/asm/mmu_context.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/include/asm/mmu_context.h = b/arch/x86/include/asm/mmu_context.h index d684b954f3c0..4f92ec3df149 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -13,6 +13,7 @@ #include #include #include +#include =20 extern atomic64_t last_mm_ctx_id; =20 @@ -358,6 +359,7 @@ static inline unsigned long = __get_current_cr3_fast(void) =20 typedef struct { struct mm_struct *prev; + unsigned short bp_enabled : 1; } temp_mm_state_t; =20 /* @@ -380,6 +382,15 @@ static inline temp_mm_state_t = use_temporary_mm(struct mm_struct *mm) lockdep_assert_irqs_disabled(); state.prev =3D this_cpu_read(cpu_tlbstate.loaded_mm); switch_mm_irqs_off(NULL, mm, current); + + /* + * If breakpoints are enabled, disable them while the temporary = mm is + * used - they do not belong and might cause wrong signals or = crashes. + */ + state.bp_enabled =3D hw_breakpoint_active(); + if (state.bp_enabled) + hw_breakpoint_disable(); + return state; } =20 @@ -387,6 +398,13 @@ static inline void = unuse_temporary_mm(temp_mm_state_t prev) { lockdep_assert_irqs_disabled(); switch_mm_irqs_off(NULL, prev.prev, current); + + /* + * Restore the breakpoints if they were disabled before the = temporary mm + * was loaded. + */ + if (prev.bp_enabled) + hw_breakpoint_restore(); } =20 #endif /* _ASM_X86_MMU_CONTEXT_H */ --=20 2.17.1