mtsr and mfsr?

mtsr and mfsr?

[Hua Ji]

Folks,

Need help, please. Thanks in advance.

I am working on a board with MPC 750 for an internal products development.

I currently can no problem set up the BATs and enable MMU for memory
management. 

However, when I set up the segment registers, I am confused and stuck here.

I was trying to clear and write some values into those 15 sr registers by
using **mtsr**.

But looks like it doesn't work. The testing I did looks like follows:

-------------
#define RESET 0 
li %r3, RESET;

sync
isync
mtsr sr0, %r3
isync
sync

mfsr %r3, sr0
bl uart_print
...
-------------

The console print-out shows that I didn't write into srs with the zero
value, except
sr1 and sr5. All the rest sr(s) value is still not back to zero.

Did I miss something?

Thanks,

Mike



 

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Re: mtsr and mfsr?

[Tom Roberts]

Hua Ji wrote:
> I was trying to clear and write some values into those 15 sr registers by
> using **mtsr**.
> But looks like it doesn't work. The testing I did looks like follows:
> #define RESET 0
> li %r3, RESET;
> 
> sync
> isync
> mtsr sr0, %r3
> isync
> sync
> 
> mfsr %r3, sr0
> bl uart_print

While the general registers are scoreboarded, the SR registers are not.
Synchronization is especially tricky between the CPU and the MMU. I suspect
that if you interchange that second "isync;sync" pair to be the usual
"sync; isync" this will work -- the "sync" ensures that the memory system
is synchronized, and the "isync" ensures that the following mfsr does not
execute until the "sync" is _complete_. But I am not certain; I do remember
this is finicky, and there may well be errors of omission in the manuals....

While "isync" says the following instructions execute in the context 
established by the preceeding instructions, I suspect that in the case of
MMU registers that really only applies to their being _used_ by the MMU, and 
not necessarily to being _read_ by the CPU.

My (non-Linux) context-switching code simply loads all SR-s and does a single
isync. It then loads all the registers (via BAT memory addressing), does a 
little bit of housekeeping (again via BAT addressing), and then does an rfi. 
At that point the SRs are all valid.

So if the above interchange does not get it to work, try inserting a
few hundred NOP-s between setting and reading sr0 (:-)).


Tom Roberts	tjroberts@Lucent.com
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