Re: [PATCH 16/16] iommupt: Add the Intel VT-D second stage page table format

[Yi Liu <yi.l.liu@intel.com>]

On 2024/8/19 23:53, Jason Gunthorpe wrote:
> On Mon, Aug 19, 2024 at 02:51:11AM +0000, Zhang, Tina wrote:
> 
>>> +/* Shared descriptor bits */
>>> +enum {
>>> +	VTDSS_FMT_R = BIT(0),
>>> +	VTDSS_FMT_W = BIT(1),
>>> +	VTDSS_FMT_X = BIT(2),
>>
>> VT-d Spec doesn't have this BIT(2) defined.
> 
> It does:
> 
>   Figure 9-8. Format for Second-Stage Paging Entries
> 
>   Bit 2 = X^1
> 
>   1. X field is ignored by hardware if Execute Request Support (ERS) is
>   reported as Clear in the Extended Capability Register or if SSEE=0 in
>   the scalable-mode PASID-table entry referencing the second-stage
>   paging entries.

it was deprecated. :( Refer to the latest spec (after 4.1). And the ERS
bit is going to be deprecated as well.

11.4.3 Extended Capability Register

"This field is planned for deprecation. Implementations must
report this field as Clear to indicate that the remapping unit does
not support requests-with-PASID that have a value of 1 in the
Execute-Requested (ER) field."

-- 
Regards,
Yi Liu