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[217.140.101.70]) by mx.google.com with ESMTP id a37si1301747edd.321.2019.02.14.07.48.01 for ; Thu, 14 Feb 2019 07:48:02 -0800 (PST) Received-SPF: pass (google.com: domain of marc.zyngier@arm.com designates 217.140.101.70 as permitted sender) client-ip=217.140.101.70; Authentication-Results: mx.google.com; spf=pass (google.com: domain of marc.zyngier@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=marc.zyngier@arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 14010EBD; Thu, 14 Feb 2019 07:48:01 -0800 (PST) Received: from [10.1.196.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id AD0BA3F575; Thu, 14 Feb 2019 07:47:59 -0800 (PST) Subject: Re: [PATCH 1/2] arm64: account for GICv3 LPI tables in static memblock reserve table To: Ard Biesheuvel , linux-efi@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Andrew Morton , James Morse , linux-mm@kvack.org References: <20190213132738.10294-1-ard.biesheuvel@linaro.org> <20190213132738.10294-2-ard.biesheuvel@linaro.org> From: Marc Zyngier Openpgp: preference=signencrypt Autocrypt: addr=marc.zyngier@arm.com; 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Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <20190213132738.10294-2-ard.biesheuvel@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: Hi Ard, On 13/02/2019 13:27, Ard Biesheuvel wrote: > In the irqchip and EFI code, we have what basically amounts to a quirk > to work around a peculiarity in the GICv3 architecture, which permits > the system memory address of LPI tables to be programmable only once > after a CPU reset. This means kexec kernels must use the same memory > as the first kernel, and thus ensure that this memory has not been > given out for other purposes by the time the ITS init code runs, which > is not very early for secondary CPUs. > > On systems with many CPUs, these reservations could overflow the > memblock reservation table, and this was addressed in commit > eff896288872 ("efi/arm: Defer persistent reservations until after > paging_init()"). However, this turns out to have made things worse, > since the allocation of page tables and heap space for the resized > memblock reservation table itself may overwrite the regions we are > attempting to reserve, which may cause all kinds of corruption, > also considering that the ITS will still be poking bits into that > memory in response to incoming MSIs. > > So instead, let's grow the static memblock reservation table on such > systems so it can accommodate these reservations at an earlier time. > This will permit us to revert the above commit in a subsequent patch. > > Signed-off-by: Ard Biesheuvel > --- > arch/arm64/include/asm/memory.h | 11 +++++++++++ > include/linux/memblock.h | 3 --- > mm/memblock.c | 10 ++++++++-- > 3 files changed, 19 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h > index e1ec947e7c0c..7e2b13cdd970 100644 > --- a/arch/arm64/include/asm/memory.h > +++ b/arch/arm64/include/asm/memory.h > @@ -332,6 +332,17 @@ static inline void *phys_to_virt(phys_addr_t x) > #define virt_addr_valid(kaddr) \ > (_virt_addr_is_linear(kaddr) && _virt_addr_valid(kaddr)) > > +/* > + * Given that the GIC architecture permits ITS implementations that can only be > + * configured with a LPI table address once, GICv3 systems with many CPUs may > + * end up reserving a lot of different regions after a kexec for their LPI > + * tables, as we are forced to reuse the same memory after kexec (and thus > + * reserve it persistently with EFI beforehand) > + */ > +#if defined(CONFIG_EFI) && defined(CONFIG_ARM_GIC_V3_ITS) > +#define INIT_MEMBLOCK_RESERVED_REGIONS (INIT_MEMBLOCK_REGIONS + 2 * NR_CPUS) Since GICv3 has 1 pending table per CPU, plus one global property table, can we make this 2 * NR_CPUS + 1? Or is that enough already? > +#endif > + > #include > > #endif > diff --git a/include/linux/memblock.h b/include/linux/memblock.h > index 64c41cf45590..859b55b66db2 100644 > --- a/include/linux/memblock.h > +++ b/include/linux/memblock.h > @@ -29,9 +29,6 @@ extern unsigned long max_pfn; > */ > extern unsigned long long max_possible_pfn; > > -#define INIT_MEMBLOCK_REGIONS 128 > -#define INIT_PHYSMEM_REGIONS 4 > - > /** > * enum memblock_flags - definition of memory region attributes > * @MEMBLOCK_NONE: no special request > diff --git a/mm/memblock.c b/mm/memblock.c > index 022d4cbb3618..a526c3ab8390 100644 > --- a/mm/memblock.c > +++ b/mm/memblock.c > @@ -26,6 +26,12 @@ > > #include "internal.h" > > +#define INIT_MEMBLOCK_REGIONS 128 > +#define INIT_PHYSMEM_REGIONS 4 > +#ifndef INIT_MEMBLOCK_RESERVED_REGIONS > +#define INIT_MEMBLOCK_RESERVED_REGIONS INIT_MEMBLOCK_REGIONS > +#endif > + > /** > * DOC: memblock overview > * > @@ -92,7 +98,7 @@ unsigned long max_pfn; > unsigned long long max_possible_pfn; > > static struct memblock_region memblock_memory_init_regions[INIT_MEMBLOCK_REGIONS] __initdata_memblock; > -static struct memblock_region memblock_reserved_init_regions[INIT_MEMBLOCK_REGIONS] __initdata_memblock; > +static struct memblock_region memblock_reserved_init_regions[INIT_MEMBLOCK_RESERVED_REGIONS] __initdata_memblock; > #ifdef CONFIG_HAVE_MEMBLOCK_PHYS_MAP > static struct memblock_region memblock_physmem_init_regions[INIT_PHYSMEM_REGIONS] __initdata_memblock; > #endif > @@ -105,7 +111,7 @@ struct memblock memblock __initdata_memblock = { > > .reserved.regions = memblock_reserved_init_regions, > .reserved.cnt = 1, /* empty dummy entry */ > - .reserved.max = INIT_MEMBLOCK_REGIONS, > + .reserved.max = INIT_MEMBLOCK_RESERVED_REGIONS, > .reserved.name = "reserved", > > #ifdef CONFIG_HAVE_MEMBLOCK_PHYS_MAP > Otherwise: Acked-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny...