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d=hostedemail.com; s=arc-20220608; t=1735960137; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=i0yhxDmQOeyIw8vfXaCGj5Eh6WuFs2uMOQxEPu5sfvU=; b=d887tNmzrVyRpl3654Ab3uFd0zfwD5PQNEYWpc3Wjl+k6mkNTJppvGG9rlyGu6sG+wxlHM WAvKdjItfDpko8LJOipRKyHj5FIJh4ysJuYQNncKf9aH22T6EYBH9We1N7q3wwcVOv4vJ1 EMq/Wm2DoDG+suD5/FaE00mM7RukHdY= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tTuWI-000000000z1-1zWE; Fri, 03 Jan 2025 22:08:10 -0500 Message-ID: <287e8a60e302929588eaf095584838fa745d69ac.camel@surriel.com> Subject: Re: [PATCH 11/12] x86/mm: enable AMD translation cache extensions From: Rik van Riel To: Jann Horn Cc: x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, akpm@linux-foundation.org, nadav.amit@gmail.com, zhengqi.arch@bytedance.com, linux-mm@kvack.org Date: Fri, 03 Jan 2025 22:08:06 -0500 In-Reply-To: References: <20241230175550.4046587-1-riel@surriel.com> <20241230175550.4046587-12-riel@surriel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) MIME-Version: 1.0 X-Stat-Signature: 3e9ordtsx6turtyhja9oj5fhtqyyqjwf X-Rspam-User: X-Rspamd-Queue-Id: 2F147A0007 X-Rspamd-Server: rspam08 X-HE-Tag: 1735960137-250741 X-HE-Meta: U2FsdGVkX18rlfs6iyvy8QJ0gPoFwfxM029N3WjcgeKXAWpD4i+U9/RTXIQG3biQayJvOOzgLS6AYOD+KmmZCThgf95dSpL3umFxIplTCdZB/KJm15bbZUH/aWdsfVWQmlkLlQyzXDOLMdZQ9hApWgZ3RQQY/qyN1wZfdskI3zbpWGchXQxoDZHJ/OXRankhMkJB/r3fycdNjifmvK8+xCmTNW7tm8TTfhzHR6DfM2n2upn3JTLUoOkDTJzDIJDZSLkKTvvKNjQVdtztUSf9S0RHw0/YlCLwF/DktKMn2RUM6Ay0AS8r5H2CUu4UjHGBlcUGzGFHfKhVDBMHamXEk+0/lnNdzMQS48w1YjJg7s7dXdGExAIj/hmM4I9AcGqx+KofojK3HwHjHTNnfhqkaN8ugUep2pZSlGbDt2XD/i15sCacgqdoT72BkishNOqLWp8TkcdrBdxVaM+yM/BPZPxRkZwCJZE4gRZ1ttS7tUm8sSoeo9oapMtkZiFq8h3HszTHAz6gyxFJ8LBkixIx9yJqu6uq9A65zSiLS+W3Z0NZ1+zJvBy+JM5sEtP1J68Qv0zM7LBr3u8gbkcNOdWKC7I/fAfhsWhS2t7m/TJkdV2iwctvTQQ22suxdcqYXnycYbjfe0uhtcKsw9HBiLA+yvaunyS++kdoaL7Pp0JUolAd7tFaWM4QOgD37qaDpO6QMzKz8R7JkKp9EFEaGKuTYpOWNpckVlVqE3j4R05tUOQ8ccioFV3i881oJ06Dy2Oq0pmXwy8IDDyi2LBENJRZmmMOX4XMB271jp2ndyNoFol+cjb3d3sh7Alg0zuH+iA+VQYNeHyle7xxuTzVjNysTaEAogR/UrdCnI1sIlgM9YGBVa6ZtDfC/pmay6G1aaw0l0JpgX11roMdCnJ/BHUnHH9d0JiBpx8DNSdSZzEXQ07m5aoAGcetnfVRG7VbkQGY3YyomImt+r7efQ9erDU kqj3fHaV M8lHTkkgRdJEJ5vf3PcjrydzbLsyFyeCdcNpHFXKQ93keEgYItTU4l8qzmzJRwMDUyr88bEMTFpFb0s75nSIMcMUJDh7qh3Zbgdc/cF4HXXAKuM33drj3l42DafqB7A/P2ynSkpQjYs+B9QIwUrv23QV8GOcZVLMDLhxdiWrq39UVGl6O74087h11Pd7AVoEKBCubpfb8TRFXqwUYvEdUmNm46jb7SGKU05XeB+MrQMzRNk8q0x9zXDU0ph2iTL9WqmhGBYb8vKMSPcEYsWXWh+Y3bHuWhu5Kq8HsaXNbj99e468pAS3b/0FQfY24eS12t4bogU9XNroTEPw8x6+IyWElNH//IZBOvSVGH3y3+Cw2S10QRYxG2xUsVrVuarfKOGyKy331c6eRd0k= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Fri, 2025-01-03 at 18:49 +0100, Jann Horn wrote: > On Mon, Dec 30, 2024 at 6:53=E2=80=AFPM Rik van Riel = =20 > > only those upper-level entries that lead to the target PTE in > > the page table hierarchy, leaving unrelated upper-level entries > > intact. >=20 > How does this patch interact with KVM SVM guests? > In particular, will this patch cause TLB flushes performed by guest > kernels to behave differently? >=20 That is a good question. A Linux guest should be fine, since Linux already flushes the parts of the TLB where page tables are being freed. I don't know whether this could potentially break some non-Linux guests, though. > [...] > > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c > > index 454a370494d3..585d0731ca9f 100644 > > --- a/arch/x86/mm/tlb.c > > +++ b/arch/x86/mm/tlb.c > > @@ -477,7 +477,7 @@ static void broadcast_tlb_flush(struct > > flush_tlb_info *info) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (info->stride_shift > PMD= _SHIFT) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 maxnr =3D 1; > >=20 > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (info->end =3D=3D TLB_FLUSH_AL= L) { > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (info->end =3D=3D TLB_FLUSH_AL= L || info->freed_tables) { > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 invlpgb_flush_single_pcid(kern_pcid(asid)); > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 /* Do any CPUs supporting INVLPGB need PTI? */ > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 if (static_cpu_has(X86_FEATURE_PTI)) > > @@ -1110,7 +1110,7 @@ static void flush_tlb_func(void *info) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * The only question is= whether to do a full or partial > > flush. > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * We do a partial flush if = requested and two extra > > conditions > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * We do a partial flush if = requested and three extra > > conditions > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * are met: > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * 1. f->new_tlb_gen = =3D=3D local_tlb_gen + 1.=C2=A0 We have an > > invariant that > > @@ -1137,10 +1137,14 @@ static void flush_tlb_func(void *info) > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *=C2=A0=C2=A0=C2=A0 da= te.=C2=A0 By doing a full flush instead, we can increase > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *=C2=A0=C2=A0=C2=A0 lo= cal_tlb_gen all the way to mm_tlb_gen and we can > > probably > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *=C2=A0=C2=A0=C2=A0 av= oid another flush in the very near future. > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 * 3. No page tables were fr= eed. If page tables were freed, > > a full > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *=C2=A0=C2=A0=C2=A0 flush e= nsures intermediate translations in the TLB > > get flushed. > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 */ >=20 > Why is this necessary - do we ever issue TLB flushes that are > intended > to zap upper-level entries which are not covered by the specified > address range? >=20 > When, for example, free_pmd_range() gets rid of a page table, it > calls > pmd_free_tlb(), which sets tlb->freed_tables and does > tlb_flush_pud_range(tlb, address, PAGE_SIZE). >=20 I missed those calls. It looks like this change is not needed. Of course, the way pmd_free_tlb() operates, the partial zaps done in that code will exceed the (default 33 pages) value of tlb_single_page_flush_ceiling, and the code in flush_tlb_mm_range() will already do a full flush by default today. I'll leave out these unnecessary changes in the next version. --=20 All Rights Reversed.