From: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
To: Zi Yan <ziy@nvidia.com>
Cc: linux-mm@kvack.org, Andrew Morton <akpm@linux-foundation.org>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Vlastimil Babka <vbabka@suse.cz>,
David Hildenbrand <david@redhat.com>,
"Matthew Wilcox (Oracle)" <willy@infradead.org>,
Miaohe Lin <linmiaohe@huawei.com>,
Kefeng Wang <wangkefeng.wang@huawei.com>,
John Hubbard <jhubbard@nvidia.com>,
"Huang, Ying" <ying.huang@linux.alibaba.com>,
Ryan Roberts <ryan.roberts@arm.com>,
Alexander Potapenko <glider@google.com>,
Kees Cook <keescook@chromium.org>,
Vineet Gupta <vgupta@kernel.org>,
linux-kernel@vger.kernel.org,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: Re: [PATCH v2] mm: use clear_user_(high)page() for arch with special user folio handling
Date: Sat, 7 Dec 2024 11:41:04 -0500 [thread overview]
Message-ID: <24442d9b-cadb-4f76-bec0-6311b1332ec1@efficios.com> (raw)
In-Reply-To: <C86620B0-E95D-4BB0-9470-FDA3422DEC8F@nvidia.com>
On 2024-12-07 11:23, Zi Yan wrote:
> On 7 Dec 2024, at 11:20, Zi Yan wrote:
[...]
>
> Or this one, which set cpu_icache_is_aliasing()’s default value
> in the generic header:
Yes, this looks good.
Just be careful to keep the same tabs vs spaces style
as the nearby code.
Thanks!
Mathieu
>
> diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
> index 5b2488142041..e96935373796 100644
> --- a/arch/arc/Kconfig
> +++ b/arch/arc/Kconfig
> @@ -6,6 +6,7 @@
> config ARC
> def_bool y
> select ARC_TIMERS
> + select ARCH_HAS_CPU_CACHE_ALIASING
> select ARCH_HAS_CACHE_LINE_SIZE
> select ARCH_HAS_DEBUG_VM_PGTABLE
> select ARCH_HAS_DMA_PREP_COHERENT
> diff --git a/arch/arc/include/asm/cachetype.h b/arch/arc/include/asm/cachetype.h
> new file mode 100644
> index 000000000000..acd3b6cb4bf5
> --- /dev/null
> +++ b/arch/arc/include/asm/cachetype.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_ARC_CACHETYPE_H
> +#define __ASM_ARC_CACHETYPE_H
> +
> +#define cpu_dcache_is_aliasing() false
> +#define cpu_icache_is_aliasing() true
> +
> +#endif
> diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
> index 108060612bb8..61a46cdff1dc 100644
> --- a/include/linux/cacheinfo.h
> +++ b/include/linux/cacheinfo.h
> @@ -155,8 +155,14 @@ static inline int get_cpu_cacheinfo_id(int cpu, int level)
>
> #ifndef CONFIG_ARCH_HAS_CPU_CACHE_ALIASING
> #define cpu_dcache_is_aliasing() false
> +#define cpu_icache_is_aliasing() cpu_dcache_is_aliasing()
> #else
> #include <asm/cachetype.h>
> +
> +#ifndef cpu_icache_is_aliasing
> +#define cpu_icache_is_aliasing() cpu_dcache_is_aliasing()
> +#endif
> +
> #endif
>
> #endif /* _LINUX_CACHEINFO_H */
>
>
> Best Regards,
> Yan, Zi
--
Mathieu Desnoyers
EfficiOS Inc.
https://www.efficios.com
next prev parent reply other threads:[~2024-12-07 16:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-06 17:42 Zi Yan
2024-12-07 15:31 ` Mathieu Desnoyers
2024-12-07 16:20 ` Zi Yan
2024-12-07 16:23 ` Zi Yan
2024-12-07 16:41 ` Mathieu Desnoyers [this message]
2024-12-07 16:38 ` Mathieu Desnoyers
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