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[2003:cb:c73b:eb00:8e25:6953:927:1802]) by smtp.gmail.com with ESMTPSA id d9-20020adffbc9000000b003367dd514d9sm554472wrs.15.2023.12.20.02.00.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 20 Dec 2023 02:00:08 -0800 (PST) Message-ID: <23638533-048f-4110-971f-bb359b39b60b@redhat.com> Date: Wed, 20 Dec 2023 11:00:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 02/16] mm: Batch-copy PTE ranges during fork() To: Ryan Roberts , Catalin Marinas , Will Deacon , Ard Biesheuvel , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Vincenzo Frascino , Andrew Morton , Anshuman Khandual , Matthew Wilcox , Yu Zhao , Mark Rutland , Kefeng Wang , John Hubbard , Zi Yan , Barry Song <21cnbao@gmail.com>, Alistair Popple , Yang Shi Cc: linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org References: <20231218105100.172635-1-ryan.roberts@arm.com> <20231218105100.172635-3-ryan.roberts@arm.com> <0bef5423-6eea-446b-8854-980e9c23a948@redhat.com> <7c0236ad-01f3-437f-8b04-125d69e90dc0@redhat.com> <9a58b1a2-2c13-4fa0-8ffa-2b3d9655f1b6@arm.com> <15177acd-8d75-46a8-9460-98ea313a7b2b@arm.com> From: David Hildenbrand Autocrypt: addr=david@redhat.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 88D2C80037 X-Rspam-User: X-Rspamd-Server: rspam04 X-Stat-Signature: cdgfy4nj38gzfp5p4wu9occ9w9uk6ako X-HE-Tag: 1703066412-571903 X-HE-Meta: U2FsdGVkX1+6BmD+7JIoB09Eq1zYv9wEgilvBUNO8/fODdK08WLOPMy3nw60zFLn02XP6cGUBeU1b2r44oP5ZxZu/PnygQnMa5EfyIiJV5OIRLT9t3QnPRkaMp4z1ryu6qRIXbLAxwpfh0shSL8JYbbNsO7cY39WYieDUIRVIpy3MDDRr6/l92V7nZHHuTFqNcNTauRN+Bs5H40ubZyPcoNbkK12/gkcczUqss0EWmzc2M5rjMu81Lrmr3v6x3f2gEH4PWgos/CEt1/co9QnZ5j4HDHFY5O0c05DOnQHLkj61ajgWVwl9Y6yTTNYrGWhvs6d9Y3+otus+LcIDNcMwR007lNZnrr8L96Vn4DEkIheGtNoL/YKnNrgGMCpNAiD9wxjdczLmMwUWnLdrkPF6Ok5QCRAADndEuUH3nJRPC0rd6FmAfcuqYmWeBzVO9nafCiR5BeNNJqop7YoA+mgfiX6pYylrn4T0TTKjWbgfS53eTVuSNykWfrOPBuqJXUBaVZ1kN4eiZoURvj6rZimkOdjLrs45SPBGi/16/lyRtmhAn3DrAibdTLt+LrH5bx5YQ8BcyIcD17Pn+NlGU8v26ZrRtSO9MqT6/DU20fnk/7+r68KbK6RzP3NN/zTJKAo4NMt+Q60R23FJd8E0EcYBtMeuGjSlTI5l+qdkPrLt4Msk9TW5fzYeg7oRY4aZBAFpNo4N0RRzQ+L7VFGiwv36ka3asWvHXw7qS5x46zla84Wur9xyyYhZ06BfbYfbZwJw0WzlZHPvivGfF8GCxtLyfIYGg5yIH+VzrdegekW7uyyJc0+rl+zSxsSKQpqhyULmpOqabHocBJFlWaGVLRdoNoNY8hv/BRPQHS+Fz1oVaCvvuMDVmymG4v8NMoST3JC/vSVgBsD3px+Cl+zfEGbaxJr1BiIlj6zR7RPKJ5GpP3OcDh7aA+HLVSUFTVeb3zq+mWG37zmm/EyiJmOu5C WsXywRPd E8h2hD5uNFgCQTKkA8N0LyZqn6dn3E9PT1l5xFN0eC/eAMAY7n5cVEAuc3Fh5KjmDCXXCkup88IZ9NBLn64q7xSrWs7KtXnYc2i5R6mXqRjekjf2DUceL3gGlQ8o4RLr+FBIRrnT1s5y8BMNabPY6FrWsDxn7Q6iaRxAGoqBTYcDaF8qj64Wmku6fUzLXmamZEKeXjiCFFZBiZsQIUlXtK5addUknPeGVsdWF7uO65eA24cVvJ77d/SR/8ZdpCHbSuieSCSIJGISUq3IrGSdVoouXizxIHyqv5vn/XsTOxWqxfqUI6tiFB6MrkDSXFgvRgS7G3/WxtymR2MsF6CQ4VPl/Jy8Whn5rAa3494srK1IQDldKB6i4Grg57nIjBmzFdoNg1TVwuux9/VXTNtqWMFFU/wlRH4svyWv8YpGWgVkv/udZp2b8MnTGO9U/mKd6i+Wz+MAVt++kFrMj5WuksNxqJhGk1cQICKgh+gHBNk1jd7BJjsJbTRjU7GES6QunW5jbbSyR2Lh5zG/BwnoI77ZzPGTPfNLYIC/JnLP7EvxALmy5jQNhYQIwfaib+ROwIHmG X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On 20.12.23 10:57, Ryan Roberts wrote: > On 20/12/2023 09:51, Ryan Roberts wrote: >> On 20/12/2023 09:17, David Hildenbrand wrote: >>> On 19.12.23 18:42, Ryan Roberts wrote: >>>> On 19/12/2023 17:22, David Hildenbrand wrote: >>>>> On 19.12.23 09:30, Ryan Roberts wrote: >>>>>> On 18/12/2023 17:47, David Hildenbrand wrote: >>>>>>> On 18.12.23 11:50, Ryan Roberts wrote: >>>>>>>> Convert copy_pte_range() to copy a batch of ptes in one go. A given >>>>>>>> batch is determined by the architecture with the new helper, >>>>>>>> pte_batch_remaining(), and maps a physically contiguous block of memory, >>>>>>>> all belonging to the same folio. A pte batch is then write-protected in >>>>>>>> one go in the parent using the new helper, ptep_set_wrprotects() and is >>>>>>>> set in one go in the child using the new helper, set_ptes_full(). >>>>>>>> >>>>>>>> The primary motivation for this change is to reduce the number of tlb >>>>>>>> maintenance operations that the arm64 backend has to perform during >>>>>>>> fork, as it is about to add transparent support for the "contiguous bit" >>>>>>>> in its ptes. By write-protecting the parent using the new >>>>>>>> ptep_set_wrprotects() (note the 's' at the end) function, the backend >>>>>>>> can avoid having to unfold contig ranges of PTEs, which is expensive, >>>>>>>> when all ptes in the range are being write-protected. Similarly, by >>>>>>>> using set_ptes_full() rather than set_pte_at() to set up ptes in the >>>>>>>> child, the backend does not need to fold a contiguous range once they >>>>>>>> are all populated - they can be initially populated as a contiguous >>>>>>>> range in the first place. >>>>>>>> >>>>>>>> This code is very performance sensitive, and a significant amount of >>>>>>>> effort has been put into not regressing performance for the order-0 >>>>>>>> folio case. By default, pte_batch_remaining() is compile constant 1, >>>>>>>> which enables the compiler to simplify the extra loops that are added >>>>>>>> for batching and produce code that is equivalent (and equally >>>>>>>> performant) as the previous implementation. >>>>>>>> >>>>>>>> This change addresses the core-mm refactoring only and a separate change >>>>>>>> will implement pte_batch_remaining(), ptep_set_wrprotects() and >>>>>>>> set_ptes_full() in the arm64 backend to realize the performance >>>>>>>> improvement as part of the work to enable contpte mappings. >>>>>>>> >>>>>>>> To ensure the arm64 is performant once implemented, this change is very >>>>>>>> careful to only call ptep_get() once per pte batch. >>>>>>>> >>>>>>>> The following microbenchmark results demonstate that there is no >>>>>>>> significant performance change after this patch. Fork is called in a >>>>>>>> tight loop in a process with 1G of populated memory and the time for the >>>>>>>> function to execute is measured. 100 iterations per run, 8 runs >>>>>>>> performed on both Apple M2 (VM) and Ampere Altra (bare metal). Tests >>>>>>>> performed for case where 1G memory is comprised of order-0 folios and >>>>>>>> case where comprised of pte-mapped order-9 folios. Negative is faster, >>>>>>>> positive is slower, compared to baseline upon which the series is based: >>>>>>>> >>>>>>>> | Apple M2 VM   | order-0 (pte-map) | order-9 (pte-map) | >>>>>>>> | fork          |-------------------|-------------------| >>>>>>>> | microbench    |    mean |   stdev |    mean |   stdev | >>>>>>>> |---------------|---------|---------|---------|---------| >>>>>>>> | baseline      |    0.0% |    1.1% |    0.0% |    1.2% | >>>>>>>> | after-change  |   -1.0% |    2.0% |   -0.1% |    1.1% | >>>>>>>> >>>>>>>> | Ampere Altra  | order-0 (pte-map) | order-9 (pte-map) | >>>>>>>> | fork          |-------------------|-------------------| >>>>>>>> | microbench    |    mean |   stdev |    mean |   stdev | >>>>>>>> |---------------|---------|---------|---------|---------| >>>>>>>> | baseline      |    0.0% |    1.0% |    0.0% |    0.1% | >>>>>>>> | after-change  |   -0.1% |    1.2% |   -0.1% |    0.1% | >>>>>>>> >>>>>>>> Tested-by: John Hubbard >>>>>>>> Reviewed-by: Alistair Popple >>>>>>>> Signed-off-by: Ryan Roberts >>>>>>>> --- >>>>>>>>     include/linux/pgtable.h | 80 +++++++++++++++++++++++++++++++++++ >>>>>>>>     mm/memory.c             | 92 ++++++++++++++++++++++++++--------------- >>>>>>>>     2 files changed, 139 insertions(+), 33 deletions(-) >>>>>>>> >>>>>>>> diff --git a/include/linux/pgtable.h b/include/linux/pgtable.h >>>>>>>> index af7639c3b0a3..db93fb81465a 100644 >>>>>>>> --- a/include/linux/pgtable.h >>>>>>>> +++ b/include/linux/pgtable.h >>>>>>>> @@ -205,6 +205,27 @@ static inline int pmd_young(pmd_t pmd) >>>>>>>>     #define arch_flush_lazy_mmu_mode()    do {} while (0) >>>>>>>>     #endif >>>>>>>>     +#ifndef pte_batch_remaining >>>>>>>> +/** >>>>>>>> + * pte_batch_remaining - Number of pages from addr to next batch boundary. >>>>>>>> + * @pte: Page table entry for the first page. >>>>>>>> + * @addr: Address of the first page. >>>>>>>> + * @end: Batch ceiling (e.g. end of vma). >>>>>>>> + * >>>>>>>> + * Some architectures (arm64) can efficiently modify a contiguous batch of >>>>>>>> ptes. >>>>>>>> + * In such cases, this function returns the remaining number of pages to >>>>>>>> the end >>>>>>>> + * of the current batch, as defined by addr. This can be useful when >>>>>>>> iterating >>>>>>>> + * over ptes. >>>>>>>> + * >>>>>>>> + * May be overridden by the architecture, else batch size is always 1. >>>>>>>> + */ >>>>>>>> +static inline unsigned int pte_batch_remaining(pte_t pte, unsigned long >>>>>>>> addr, >>>>>>>> +                        unsigned long end) >>>>>>>> +{ >>>>>>>> +    return 1; >>>>>>>> +} >>>>>>>> +#endif >>>>>>> >>>>>>> It's a shame we now lose the optimization for all other archtiectures. >>>>>>> >>>>>>> Was there no way to have some basic batching mechanism that doesn't require >>>>>>> arch >>>>>>> specifics? >>>>>> >>>>>> I tried a bunch of things but ultimately the way I've done it was the only way >>>>>> to reduce the order-0 fork regression to 0. >>>>>> >>>>>> My original v3 posting was costing 5% extra and even my first attempt at an >>>>>> arch-specific version that didn't resolve to a compile-time constant 1 still >>>>>> cost an extra 3%. >>>>>> >>>>>> >>>>>>> >>>>>>> I'd have thought that something very basic would have worked like: >>>>>>> >>>>>>> * Check if PTE is the same when setting the PFN to 0. >>>>>>> * Check that PFN is consecutive >>>>>>> * Check that all PFNs belong to the same folio >>>>>> >>>>>> I haven't tried this exact approach, but I'd be surprised if I can get the >>>>>> regression under 4% with this. Further along the series I spent a lot of time >>>>>> having to fiddle with the arm64 implementation; every conditional and every >>>>>> memory read (even when in cache) was a problem. There is just so little in the >>>>>> inner loop that every instruction matters. (At least on Ampere Altra and Apple >>>>>> M2). >>>>>> >>>>>> Of course if you're willing to pay that 4-5% for order-0 then the benefit to >>>>>> order-9 is around 10% in my measurements. Personally though, I'd prefer to play >>>>>> safe and ensure the common order-0 case doesn't regress, as you previously >>>>>> suggested. >>>>>> >>>>> >>>>> I just hacked something up, on top of my beloved rmap cleanup/batching series. I >>>>> implemented very generic and simple batching for large folios (all PTE bits >>>>> except the PFN have to match). >>>>> >>>>> Some very quick testing (don't trust each last % ) on Intel(R) Xeon(R) Silver >>>>> 4210R CPU. >>>>> >>>>> order-0: 0.014210 -> 0.013969 >>>>> >>>>> -> Around 1.7 % faster >>>>> >>>>> order-9: 0.014373 -> 0.009149 >>>>> >>>>> -> Around 36.3 % faster >>>> >>>> Well I guess that shows me :) >>>> >>>> I'll do a review and run the tests on my HW to see if it concurs. >>> >>> >>> I pushed a simple compile fixup (we need pte_next_pfn()). >> >> I've just been trying to compile and noticed this. Will take a look at your update. > > Took a look; there will still be arch work needed; arm64 doesn't define > PFN_PTE_SHIFT because it defines set_ptes(). I'm not sure if there are other > arches that also don't define PFN_PTE_SHIFT (or pte_next_pfn()) if the math is > more complex) - it will need an audit. > Right, likely many that have their own set_ptes() implementation right now. -- Cheers, David / dhildenb