Re: [PATCH] arm64: contpte: fix set_access_flags() no-op check for SMMU/ATS faults

[Jason Gunthorpe <jgg@nvidia.com>]

On Wed, Mar 04, 2026 at 03:01:51PM +0000, Catalin Marinas wrote:
> Good point. For the AF bit, the hardware is not allowed to cache it in
> the TLB, so we can't get an AF fault for an unrelated VA nearby.

The way we have read the spec is there is no restriction on what PTE
the HW accesses when it encounters a CONT group.

To be concrete, the spec seems to say it is legal to make HW that
fetches the PTE at the VA, sees the CONT bit, and then always fetches
the 0th PTE from the group and only uses that for permission checks.

Therefore SW should never assume that HW will read any particular
sub-PTE under any scenario.

It seems current cores don't do this, and it is a bit silly to do, but
I can imagine an optimizion where the core does a cache line fetch to
read the PTE so it can freely snap to the PTE at the start of the
cache line for permission checks. Consolidating permission storage to
fewer PTEs would reduce atomic memory traffic if the TLB is thrashing.

Jason