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Wed, 4 Feb 2026 13:44:48 +0000 Date: Wed, 4 Feb 2026 13:44:47 +0000 From: Jonathan Cameron To: Linus Walleij CC: Yushan Wang , , , , , , , , , , , , , , , SeongJae Park , Subject: Re: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC Message-ID: <20260204134447.00000afd@huawei.com> In-Reply-To: <20260204134020.00002393@huawei.com> References: <20260203161843.649417-1-wangyushan12@huawei.com> <20260203161843.649417-2-wangyushan12@huawei.com> <20260204134020.00002393@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml100011.china.huawei.com (7.191.174.247) To dubpeml500005.china.huawei.com (7.214.145.207) X-Stat-Signature: qoumrb8nhiew9dxg86qw9hy9hmxpims1 X-Rspam-User: X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: BD23D100016 X-HE-Tag: 1770212695-200926 X-HE-Meta: U2FsdGVkX194q3jdqoU/n8fndtphJCiZEWtd8Rrrtj67aqR/7aZelv8qs6y8whnFrpNXztm0ECsfdk9vH47fa7MhUGiJZP4vtfgGjTaxRTdb4pK2kNI2u7G1xe/+AZVHUQeYX4lQ91P9BS5mzc8ZYXQqL/Qr9kCaid8GWf3hHlz18ICAwn3jfahqd5pB7lRqAMAMtvttPvkAs+SK3I8fwiuWhgkASiENLkorphN12DsUn4xNO019Gs8kviNch1TW0GwgVfya5eSSfAd/iN4WmjAm3R8qfiOH4kCD8L6k4oOOd2bbP4xnNZ9b+WwpqsbbvtJrOalktA5byXiNCyu6OeRzvuvwR1ezF15bYfpTu1nvpjVnvcjzeXRjnVd6ag/u9pxS1+ciXhUUyK16mfkBzNBRIjS3isGVCQvvRdMP/7BROY3tCduh3ogDdI05phDKI2U6WcmJdrvtsTQMY9rAXfkqp4nh2zcq+b31OEUPvqxVqu4Cd9WB8Ncikp94LkUJ7bZ1RKXIuGuaVh/X1Yh7+gHFPrl6Cd3aiFY/ZruTxLRXq4sj1bkHWQcWSuA3at+pzADLqLP3XnxNSdcxY99PlHfR0z18/KS5M66djH0Wt9xY09+qd15CewT8tar82WFXCRJR94KZ6O/jid5n4HzD+ieGjvEDhHmiopgVstLILN56QTL73siGpweN7FFXRKR9Ewl0qBzqUvzk5yfFl8lRbbCQGfeCqsDhIVUccDprkDeF1P1fERNULajatV6j01r9Gc+4yk43msSVDVWLQ/BJyC7zQ1hS3zaTZUWS3LfVSHPrvDlO/MarC2rjhc4clQ13E4ELul7Mpq5EdM0sSRmLlzNKNqSZdwLhzT5HZiIijLiq6zpmHh8PRrBkHR/xTSGZ+gX3w34SSqGUifkwE96zuCq4joZ05zYzeO/UufHaPSqsS3qgam2vV4b9FXF2I11GFsauav0E8KFE5JXBPwy y+0Y6x6F o/FgGFVWAtkhyVwb82bycz/eD8XnGOtddrGukA/lJSeJT9wpDVlsgtJKxv5dxho6ExTTclOpJ3swGmgEs/BG3FYLFlmD0SkW4DXj24lP8WylS4dwuQO54jx88V5GqgLQJsK5XZCtYxiYFK9scFdJgbGYUqlE5zJlFYvwLHR3oq/glKmSSNRgug4XjUVWb8u0ZcBtbRS3A7svNXyIoH0ZsXn6IhGq2qrrLkkWDXPr/05D1joudAKCdIVx5ResbeL5C1xFu X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Fixed linux-mm address that got added a few emails back. On Wed, 4 Feb 2026 13:40:20 +0000 Jonathan Cameron wrote: > On Wed, 4 Feb 2026 01:10:01 +0100 > Linus Walleij wrote: >=20 > > Hi Yushan, > >=20 > > thanks for your patch! > >=20 > > On Tue, Feb 3, 2026 at 5:18=E2=80=AFPM Yushan Wang wrote: =20 > > > > > > The driver will create a file of `/dev/hisi_l3c` on init, mmap > > > operations to it will allocate a memory region that is guaranteed to = be > > > placed in L3 cache. > > > > > > The driver also provides unmap() to deallocated the locked memory. > > > > > > The driver also provides an ioctl interface for user to get cache lock > > > information, such as lock restrictions and locked sizes. > > > > > > Signed-off-by: Yushan Wang =20 > >=20 > > The commit message does not say *why* you are doing this? > > =20 > > > +config HISI_SOC_L3C > > > + bool "HiSilicon L3 Cache device driver" > > > + depends on ACPI > > > + depends on ARM64 || COMPILE_TEST > > > + help > > > + This driver provides the functions to lock L3 cache entries= from > > > + being evicted for better performance. =20 > >=20 > > Here is the reason though. > >=20 > > Things like this need to be CC to linux-mm@vger.kernel.org. > >=20 > > I don't see why userspace would be so well informed as to make decisions > > about what should be locked in the L3 cache and not? > >=20 > > I see the memory hierarchy as any other hardware: a resource that is > > allocated and arbitrated by the kernel. > >=20 > > The MM subsytem knows which memory is most cache hot. > > Especially when you use DAMON DAMOS, which has the sole > > purpose of executing actions like that. Here is a good YouTube. > > https://www.youtube.com/watch?v=3DxKJO4kLTHOI =20 > Hi Linus, >=20 > This typically isn't about cache hot. It it were, the data would > be in the cache without this. It's about ensuring something that would > otherwise unlikely to be there is in the cache. >=20 > Normally that's a latency critical region. In general the kernel > has no chance of figuring out what those are ahead of time, only > userspace can know (based on profiling etc) that is per workload. > The first hit matters in these use cases and it's not something > the prefetchers can help with. >=20 > The only thing we could do if this was in kernel would be to > have userspace pass some hints and then let the kernel actually > kick off the process. That just boils down to using a different > interface to do what this driver is doing (and that's the conversaion > this series is trying to get going) It's a finite resource > and you absolutely need userspace to be able to tell if it > got what it asked for or not. >=20 > Damon might be useful for that preanalysis though but it can't do > anything for the infrequent extremely latency sensitive accesses. > Normally this is fleet wide stuff based on intensive benchmarking > of a few nodes. Same sort of approach as the original warehouse > scale computing paper on tuning zswap capacity across a fleet. > Its an extreme form of profile guided optimization (and not > currently automatic I think?). If we are putting code in this > locked region, the program has been carefully recompiled / linked > to group the critical parts so that we can use the minimum number > of these locked regions. Data is a little simpler. >=20 > It's kind of similar to resctl but at a sub process granularity. >=20 > >=20 > > Shouldn't the MM subsystem be in charge of determining, locking > > down and freeing up hot regions in L3 cache? > >=20 > > This looks more like userspace is going to determine that but > > how exactly? By running DAMON? Then it's better to keep the > > whole mechanism in the kernel where it belongs and let the > > MM subsystem adapt locked L3 cache to the usage patterns. =20 >=20 > I haven't yet come up with any plausible scheme by which the MM > subsystem could do this. >=20 > I think what we need here Yushan, is more detail on end to end > use cases for this. Some examples etc as clearer motivation. >=20 > Jonathan >=20 > >=20 > > Yours, > > Linus Walleij > > =20 >=20