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From: Rik van Riel <riel@surriel.com>
To: linux-kernel@vger.kernel.org
Cc: linux-mm@kvack.org, x86@kernel.org, dave.hansen@linux.intel.com,
	peterz@infradead.org, kernel-team@meta.com, bp@alien8.de,
	Yu-cheng Yu <yu-cheng.yu@intel.com>,
	Rik van Riel <riel@surriel.com>
Subject: [RFC v5 1/8] x86/mm: Introduce Remote Action Request MSRs
Date: Fri, 21 Nov 2025 13:54:22 -0500	[thread overview]
Message-ID: <20251121185530.21876-2-riel@surriel.com> (raw)
In-Reply-To: <20251121185530.21876-1-riel@surriel.com>

From: Yu-cheng Yu <yu-cheng.yu@intel.com>

Remote Action Request (RAR) is a model-specific feature to speed
up inter-processor operations by moving parts of those operations
from software to hardware.

The current RAR implementation handles TLB flushes and MSR writes.

This patch introduces RAR MSRs.  RAR is introduced in later patches.

There are five RAR MSRs:

  MSR_CORE_CAPABILITIES
  MSR_IA32_RAR_CTRL
  MSR_IA32_RAR_ACT_VEC
  MSR_IA32_RAR_PAYLOAD_BASE
  MSR_IA32_RAR_INFO

Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rik van Riel <riel@surriel.com>
---
 arch/x86/include/asm/msr-index.h | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3d0a0950d20a..69d9e96e8324 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -110,6 +110,8 @@
 
 /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
 #define MSR_IA32_CORE_CAPS			  0x000000cf
+#define MSR_IA32_CORE_CAPS_RAR_BIT		  1
+#define MSR_IA32_CORE_CAPS_RAR			  BIT(MSR_IA32_CORE_CAPS_RAR_BIT)
 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT	  2
 #define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS	  BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
 #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
@@ -122,6 +124,17 @@
 #define SNB_C3_AUTO_UNDEMOTE		(1UL << 27)
 #define SNB_C1_AUTO_UNDEMOTE		(1UL << 28)
 
+/*
+ * Remote Action Requests (RAR) MSRs
+ */
+#define MSR_IA32_RAR_CTRL		0x000000ed
+#define MSR_IA32_RAR_ACT_VEC		0x000000ee
+#define MSR_IA32_RAR_PAYLOAD_BASE	0x000000ef
+#define MSR_IA32_RAR_INFO		0x000000f0
+
+#define RAR_CTRL_ENABLE			BIT(31)
+#define RAR_CTRL_IGNORE_IF		BIT(30)
+
 #define MSR_MTRRcap			0x000000fe
 
 #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
-- 
2.51.1



  reply	other threads:[~2025-11-21 18:55 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-21 18:54 [RFC v5 0/8] x86/mm: Intel RAR TLB invalidation support Rik van Riel
2025-11-21 18:54 ` Rik van Riel [this message]
2025-11-21 18:54 ` [RFC v5 2/8] x86/mm: enable BROADCAST_TLB_FLUSH on Intel, too Rik van Riel
2025-11-21 18:54 ` [RFC v5 3/8] x86/mm: Introduce X86_FEATURE_RAR Rik van Riel
2025-11-21 18:54 ` [RFC v5 4/8] x86/apic: Introduce Remote Action Request Operations Rik van Riel
2025-11-21 18:54 ` [RFC v5 5/8] x86/mm: Introduce Remote Action Request Rik van Riel
2025-11-21 18:54 ` [RFC v5 6/8] x86/mm: use RAR for kernel TLB flushes Rik van Riel
2025-11-21 18:54 ` [RFC v5 7/8] x86/mm: userspace & pageout flushing using Intel RAR Rik van Riel
2025-11-21 18:54 ` [RFC v5 8/8] x86/mm: make RAR invalidation scalable by skipping duplicate APIC pokes Rik van Riel

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