On Fri, Nov 14, 2025 at 12:49:58PM +0000, Jonathan Cameron wrote: > On Sat, 8 Nov 2025 20:02:52 +0000 > Conor Dooley wrote: > > > Arnd, > > > > On Fri, Oct 31, 2025 at 11:17:03AM +0000, Jonathan Cameron wrote: > > > Support system level interfaces for cache maintenance as found on some > > > ARM64 systems. It is expected that systems using other CPU architectures > > > (such as RiscV) that support CXL memory and allow for native OS flows > > > will also use this. This is needed for correct functionality during > > > various forms of memory hotplug (e.g. CXL). Typical hardware has MMIO > > > interface found via ACPI DSDT. A system will often contain multiple > > > hardware instances. > > > > > > Includes parameter changes to cpu_cache_invalidate_memregion() but no > > > functional changes for architectures that already support this call. > > > > > > How to merge? > > > - Current suggestion would be via Conor's drivers/cache tree which routes > > > through the SoC tree. > > > > I was gonna put this in linux-next, but I'm not really sure that Arnd > > was satisfied with the discussion on the previous version about > > suitability of the directory: https://lore.kernel.org/all/20251028114348.000006ed@huawei.com/ > > > > Arnd, did that response satisfy you, or nah? > > Seems Arnd is busy. Conor, if you are happy doing so, maybe push it to a tree > linux-next picks up, but hold off on the pull request until Arnd has had a chance > to reply? Yeah, I did step one of that last night and will put it in linux-next from Monday. Ultimately the PR goes to Arnd, so he can judge it there anyway.