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Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Andreas Hindborg , Alice Ryhl , Trevor Gross , Benno Lossin Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Deepak Gupta X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761238267; l=2296; i=debug@rivosinc.com; s=20251023; h=from:subject:message-id; bh=kcKAh3qiYa6u+vavoC8VVP4XbgP0FdaLB3/LKiPnoo8=; b=5abQ/8Fyb67brrslHsppHvVHhbfMSh362P9OdeCdOVQdtEtbY5fxaIbvhvl5q8aWJDf/FV0Fq fHseZWEX8HbDzUjvYtlSnv7SPpsB46CG4aJqGJvIu5MxcK1mzpPlmzq X-Developer-Key: i=debug@rivosinc.com; a=ed25519; pk=O37GQv1thBhZToXyQKdecPDhtWVbEDRQ0RIndijvpjk= X-Endpoint-Received: by B4 Relay for debug@rivosinc.com/20251023 with auth_id=553 X-Original-From: Deepak Gupta Reply-To: debug@rivosinc.com X-Stat-Signature: 39hs9dswr5a1jwpyjx3gcijcyygq7jje X-Rspamd-Queue-Id: 685E4A0007 X-Rspamd-Server: rspam06 X-Rspam-User: X-HE-Tag: 1761238272-156993 X-HE-Meta: U2FsdGVkX19oAODTxyEBAhCKy36ZQG2j4PmbRf0ssncknJcgeXVLXmxpex8nbQMfVHCa53FPHsy3x2r0Ers2NfwSyF4Sd+l33q9Gw38/MMyuSDucEmm6JlSNrLrfHbJJIYIqhEmCpc9XyusYk7mmUaWTu9pc9i2+CClYiwJU41TtpwPclQFHeQ1fc0wA4zBBC2qjcRFrpy3nb3bp7zHFqkFyhuHzk8xvjlPj4VyhA+xWaIjVunAQpZVulwXFZzwYcar2pzHmf6pC/cNciUkaxpt+rDRkH0SRoAO6mCmxB78iEqzAFn6JY+ofqWil059P5L5Z5jJvU8zDG/sgU2bjjzQt+vVlPvVBtTStUON9KIiwKqtL6xm+TfPaWnv/TZmFOAlkRiuWzQme7+Uu77NLgoMvgPWyiR/JtG+3OdVKIeF4CcQK+1E62sBUPtCIfMt7lVPXgCMHBamU3m9rip6yEh7KBEnfyrnJ3h1rekZ6WCVRdXBJxSp82K/QGt3iVlT9A1yCLZdt6IPkT83oN2pC6NT5bQ47gDb5cIxcwU5zZeLQ2wvDkOvVFitw/g9hKXQFvyMIBGplaTUjVyKpQHIMT9Rg542lEGVpad91JkJFVudlOokoi3Hu3x5g+3wtxw/UiQE2i6oCuFOBdNVN9YF+g99LVHfZXU1HmVLvXBvr0VnkAHmsREKELQ97Lkg0W1auDFz73uZl0oSJeNzI5IXVftHyw0gaZz9eq7voVEgKClfM78OYITpYS35tAHG4DTMC/gxnbuzeqjxxStThnZuKqD1V33xWASSCdb3tMuvDROj7xINDmrxgXF3u1q7/mbPTvfHRNWyxfIojbIGa7K/i2OJRxGB2tMCaGGj2eqUqvz0+Zuwk8JgscKJDBci9NAcDd12JhSEYIeBlAqkhEH5cP7NhQtWD27FtSFve9JMfyhBYgPKygBVmY1p1J2gcgTpcoPBqJi5N/7PB9p05rk5 vxFYiuLJ J0Clp8WWKZ0KL5QbPTKm7n4/EY8c1LysjLbUFjRYyRCA7WkVb5QBodbhxn0BlJz0gI5XXAIERutN3ZLp3H/n6+MVxWiq0N0efNh9xkkFQUMKDOUAnvwwwr/yR+xDs24XZKKe7Sg+Tov9XsB6j4G8yIuTsqdnLhIFNldq+rYdhj6Ke+vPmIABF7fAwZ5SHS5y3aXXy8P0nhGHvKtcfsyRB1ctLiFyqDOqN4cWs0ePfaxHIOgKI/fVD4b8mhKpiCOxUdfc3NRyWYdZ7aS87fw0F8RbcSX46jXHJqm4ivAJlF6j+f201biRHXmhbM+pdOsNXIr7YzJJrPsxO7XwuXI3CsNHP5ypNrijGySQvpBpC0jKkUHRS9jb8EtQauYbBSieRIEcNSspO+z8CN2rakwG4M2lTMroAazf+MFQLxgJ09M0UA4qaEaRR2WgPQKz54tqkkkRv3UsUf9/wPk4f+4FxunVqfNXI41LKCdx2 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: From: Deepak Gupta zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while senvcfg controls enabling for U/VU mode. zicfilp extension extends *status CSR to hold `expected landing pad` bit. A trap or interrupt can occur between an indirect jmp/call and target instr. `expected landing pad` bit from CPU is recorded into xstatus CSR so that when supervisor performs xret, `expected landing pad` state of CPU can be restored. zicfiss adds one new CSR - CSR_SSP: CSR_SSP contains current shadow stack pointer. Signed-off-by: Deepak Gupta Reviewed-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 4a37a98398ad..78f573ab4c53 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -18,6 +18,15 @@ #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ +/* zicfilp landing pad status bit */ +#define SR_SPELP _AC(0x00800000, UL) +#define SR_MPELP _AC(0x020000000000, UL) +#ifdef CONFIG_RISCV_M_MODE +#define SR_ELP SR_MPELP +#else +#define SR_ELP SR_SPELP +#endif + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ #define SR_FS_OFF _AC(0x00000000, UL) #define SR_FS_INITIAL _AC(0x00002000, UL) @@ -212,6 +221,8 @@ #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) +#define ENVCFG_LPE (_AC(1, UL) << 2) +#define ENVCFG_SSE (_AC(1, UL) << 3) #define ENVCFG_CBIE_SHIFT 4 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) #define ENVCFG_CBIE_ILL _AC(0x0, UL) @@ -230,6 +241,11 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* + * zicfiss user mode csr + * CSR_SSP holds current shadow stack pointer. + */ +#define CSR_SSP 0x011 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM -- 2.43.0