From: Andrew Morton <akpm@linux-foundation.org>
To: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Conor Dooley <conor@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
<linux-cxl@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-arch@vger.kernel.org>, <linux-mm@kvack.org>,
Dan Williams <dan.j.williams@intel.com>,
"H . Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>, <james.morse@arm.com>,
Will Deacon <will@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>, <linuxarm@huawei.com>,
Yushan Wang <wangyushan12@huawei.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
<x86@kernel.org>, Andy Lutomirski <luto@kernel.org>,
Dave Jiang <dave.jiang@intel.com>
Subject: Re: [PATCH v4 0/6] Cache coherency management subsystem
Date: Wed, 22 Oct 2025 12:22:41 -0700 [thread overview]
Message-ID: <20251022122241.d2aa0d7864f67112aa7691bf@linux-foundation.org> (raw)
In-Reply-To: <20251022113349.1711388-1-Jonathan.Cameron@huawei.com>
On Wed, 22 Oct 2025 12:33:43 +0100 Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> Support system level interfaces for cache maintenance as found on some
> ARM64 systems. This is needed for correct functionality during various
> forms of memory hotplug (e.g. CXL). Typical hardware has MMIO interface
> found via ACPI DSDT.
>
> Includes parameter changes to cpu_cache_invalidate_memregion() but no
> functional changes for architectures that already support this call.
I see additions to lib/ so presumably there is an expectation that
other architectures might use this.
Please expand on this. Any particular architectures in mind? Any
words of wisdom which maintainers of those architectures might benefit
from?
> How to merge? When this is ready to proceed (so subject to review
> feedback on this version), I'm not sure what the best route into the
> kernel is. Conor could take the lot via his tree for drivers/cache but
> the generic changes perhaps suggest it might be better if Andrew
> handles this? Any merge conflicts in drivers/cache will be trivial
> build file stuff. Or maybe even take it throug one of the affected
> trees such as CXL.
Let's not split the series up. Either CXL or COnor's tree is fine my
me.
next prev parent reply other threads:[~2025-10-22 19:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 11:33 Jonathan Cameron
2025-10-22 11:33 ` [PATCH v4 1/6] memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() Jonathan Cameron
2025-10-22 11:33 ` [PATCH v4 2/6] memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() Jonathan Cameron
2025-10-22 11:33 ` [PATCH v4 3/6] lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-10-22 21:11 ` Conor Dooley
2025-10-23 11:13 ` Jonathan Cameron
2025-10-22 11:33 ` [PATCH v4 4/6] arm64: Select GENERIC_CPU_CACHE_MAINTENANCE Jonathan Cameron
2025-10-22 11:33 ` [PATCH v4 5/6] MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header Jonathan Cameron
2025-10-22 11:33 ` [PATCH v4 6/6] cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent Jonathan Cameron
2025-10-22 21:39 ` Conor Dooley
2025-10-23 11:49 ` Jonathan Cameron
2025-10-23 17:58 ` Conor Dooley
2025-10-22 19:22 ` Andrew Morton [this message]
2025-10-22 20:47 ` [PATCH v4 0/6] Cache coherency management subsystem Conor Dooley
2025-10-23 16:40 ` Jonathan Cameron
2025-10-27 9:44 ` Arnd Bergmann
2025-10-28 11:43 ` Jonathan Cameron
2025-10-23 12:31 ` Jonathan Cameron
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