On Wed, Oct 22, 2025 at 12:33:46PM +0100, Jonathan Cameron wrote: > From: Yicong Yang > > ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION provides the mechanism for > invalidating certain memory regions in a cache-incoherent manner. Currently > this is used by NVDIMM and CXL memory drivers in cases where it is > necessary to flush all data from caches by physical address range. > > In some architectures these operations are supported by system components > that may become available only later in boot as they are either present > on a discoverable bus, or via a firmware description of an MMIO interface > (e.g. ACPI DSDT). Provide a framework to handle this case. > > Architectures can opt in for this support via > CONFIG_GENERIC_CPU_CACHE_MAINTENANCE > > Add a registration framework. Each driver provides an ops structure and > the first op is Write Back and Invalidate by PA Range. The driver may > over invalidate. > > An optional completion check operation is also provided. If present > that should be called to ensure that the action has finished. > > When multiple agents are present in the system each should register with > this framework and the core code will issue the invalidate to all of them > before checking for completion on each. This is done to avoid need for > filtering in the core code which can become complex when interleave, > potentially across different cache coherency hardware is going on, so it > is easier to tell everyone and let those who don't care do nothing. > > Signed-off-by: Yicong Yang > Co-developed-by: Jonathan Cameron > Signed-off-by: Jonathan Cameron Acked-by: Conor Dooley I'm fine with this stuff. I do wonder though, have you actually encountered systems with the multiple "agents" or is that something theoretical?