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From: Jason Gunthorpe <jgg@nvidia.com>
To: "Liam R. Howlett" <Liam.Howlett@oracle.com>,
	ankita@nvidia.com, aniketa@nvidia.com, vsethi@nvidia.com,
	mochs@nvidia.com, skolothumtho@nvidia.com, linmiaohe@huawei.com,
	nao.horiguchi@gmail.com, akpm@linux-foundation.org,
	david@redhat.com, lorenzo.stoakes@oracle.com, vbabka@suse.cz,
	rppt@kernel.org, surenb@google.com, mhocko@suse.com,
	tony.luck@intel.com, bp@alien8.de, rafael@kernel.org,
	guohanjun@huawei.com, mchehab@kernel.org, lenb@kernel.org,
	kevin.tian@intel.com, alex@shazbot.org, cjia@nvidia.com,
	kwankhede@nvidia.com, targupta@nvidia.com, zhiw@nvidia.com,
	dnigam@nvidia.com, kjaju@nvidia.com,
	linux-kernel@vger.kernel.org, linux-mm@kvack.org,
	linux-edac@vger.kernel.org, Jonathan.Cameron@huawei.com,
	ira.weiny@intel.com, Smita.KoralahalliChannabasappa@amd.com,
	u.kleine-koenig@baylibre.com, peterz@infradead.org,
	linux-acpi@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 0/3] mm: Implement ECC handling for pfn with no struct page
Date: Tue, 21 Oct 2025 13:44:44 -0300	[thread overview]
Message-ID: <20251021164444.GB699957@nvidia.com> (raw)
In-Reply-To: <hbk4hqrdaz7qipkpb5g2znhva63sghwsiqwlyf6pb6xccjtp47@vci5e4vbkjqo>

On Tue, Oct 21, 2025 at 12:30:48PM -0400, Liam R. Howlett wrote:
> > enables VM_PFNMAP vmas to map at PMD level. Otherwise, a poison to a PFN
> > would need breaking the PMD mapping into PTEs to unmap only the poisoned
> > PFN. This can have a major performance impact.
> 
> Is the performance impact really a concern in the event of failed
> memory? 

Yes, something like the KVM S2 is very sensitive to page size for TLB
performace.

> Does this happen enough to warrant this special case?

If you have a 100k sized cluster it happens constantly :\

> Surely it's not failing hardware that may cause performance impacts, so
> is this triggered in some other way that I'm missing or a conversation
> pointer?

It is the splitting of a pgd/pmd level into PTEs that gets mirrored
into the S2 and then greatly increases the cost of table walks inside
a guest. The HW caches are sized for 1G S2 PTEs, not 4k.

Jason


  reply	other threads:[~2025-10-21 16:44 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-21 10:23 ankita
2025-10-21 10:23 ` [PATCH v3 1/3] mm: handle poisoning of pfn without struct pages ankita
2025-10-21 17:05   ` Ira Weiny
2025-10-22 16:00   ` Jiaqi Yan
2025-10-24  6:34   ` Miaohe Lin
2025-10-24  9:45   ` Shuai Xue
2025-10-24 11:52     ` Jason Gunthorpe
2025-10-24 11:59       ` Ankit Agrawal
2025-10-21 10:23 ` [PATCH v3 2/3] mm: Change ghes code to allow poison of non-struct pfn ankita
2025-10-21 17:13   ` Ira Weiny
2025-10-21 17:19     ` Luck, Tony
2025-10-22  6:53       ` Shuai Xue
2025-10-22 15:03         ` Ira Weiny
2025-10-24 10:03           ` Shuai Xue
2025-10-24 11:26             ` Ankit Agrawal
2025-10-21 10:23 ` [PATCH v3 3/3] vfio/nvgrace-gpu: register device memory for poison handling ankita
2025-10-21 16:30 ` [PATCH v3 0/3] mm: Implement ECC handling for pfn with no struct page Liam R. Howlett
2025-10-21 16:44   ` Jason Gunthorpe [this message]
2025-10-21 18:54     ` Liam R. Howlett
2025-10-21 22:38       ` Jason Gunthorpe
2025-10-24 11:16         ` Ankit Agrawal

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