From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>,
linux-riscv@lists.infradead.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, Conor Dooley <conor@kernel.org>,
Alexandre Ghiti <alex@ghiti.fr>,
Emil Renner Berthing <kernel@esmil.dk>,
Andrew Morton <akpm@linux-foundation.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>
Subject: [PATCH v2 08/18] riscv: mm: Simplify set_p4d() and set_pgd()
Date: Wed, 8 Oct 2025 18:57:44 -0700 [thread overview]
Message-ID: <20251009015839.3460231-9-samuel.holland@sifive.com> (raw)
In-Reply-To: <20251009015839.3460231-1-samuel.holland@sifive.com>
RISC-V uses the same page table entry format and has the same atomicity
requirements at all page table levels, so these setter functions use the
same underlying implementation at all levels. Checking the translation
mode to pick between two identical branches only serves to make these
functions less efficient.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
Changes in v2:
- New patch for v2
arch/riscv/include/asm/pgtable-64.h | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 1018d22169013..7eb23c24310f9 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -273,10 +273,7 @@ static inline unsigned long _pmd_pfn(pmd_t pmd)
static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
{
- if (pgtable_l4_enabled)
- WRITE_ONCE(*p4dp, p4d);
- else
- set_pud((pud_t *)p4dp, (pud_t){ p4d_val(p4d) });
+ WRITE_ONCE(*p4dp, p4d);
}
static inline int p4d_none(p4d_t p4d)
@@ -340,10 +337,7 @@ pud_t *pud_offset(p4d_t *p4d, unsigned long address);
static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
{
- if (pgtable_l5_enabled)
- WRITE_ONCE(*pgdp, pgd);
- else
- set_p4d((p4d_t *)pgdp, (p4d_t){ pgd_val(pgd) });
+ WRITE_ONCE(*pgdp, pgd);
}
static inline int pgd_none(pgd_t pgd)
--
2.47.2
next prev parent reply other threads:[~2025-10-09 1:59 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 1:57 [PATCH v2 00/18] riscv: Memory type control for platforms with physical memory aliases Samuel Holland
2025-10-09 1:57 ` [PATCH v2 01/18] mm/ptdump: Replace READ_ONCE() with standard page table accessors Samuel Holland
2025-10-09 9:34 ` David Hildenbrand
2025-10-09 1:57 ` [PATCH v2 02/18] perf/core: " Samuel Holland
2025-10-09 2:03 ` Anshuman Khandual
2025-10-09 1:57 ` [PATCH v2 03/18] mm: Move the fallback definitions of pXXp_get() Samuel Holland
2025-10-09 1:57 ` [PATCH v2 04/18] mm: Always use page table accessor functions Samuel Holland
2025-10-09 2:10 ` Anshuman Khandual
2025-10-09 1:57 ` [PATCH v2 05/18] mm: Allow page table accessors to be non-idempotent Samuel Holland
2025-10-09 1:57 ` [PATCH v2 06/18] riscv: hibernate: Replace open-coded pXXp_get() Samuel Holland
2025-10-09 1:57 ` [PATCH v2 07/18] riscv: mm: Always use page table accessor functions Samuel Holland
2025-10-09 1:57 ` Samuel Holland [this message]
2025-10-09 1:57 ` [PATCH v2 09/18] riscv: mm: Deduplicate _PAGE_CHG_MASK definition Samuel Holland
2025-10-09 1:57 ` [PATCH v2 10/18] riscv: ptdump: Only show N and MT bits when enabled in the kernel Samuel Holland
2025-10-09 1:57 ` [PATCH v2 11/18] riscv: mm: Fix up memory types when writing page tables Samuel Holland
2025-10-09 1:57 ` [PATCH v2 12/18] riscv: mm: Expose all page table bits to assembly code Samuel Holland
2025-10-09 1:57 ` [PATCH v2 13/18] riscv: alternative: Add an ALTERNATIVE_3 macro Samuel Holland
2025-10-09 1:57 ` [PATCH v2 14/18] riscv: alternative: Allow calls with alternate link registers Samuel Holland
2025-10-09 1:57 ` [PATCH v2 15/18] dt-bindings: riscv: Describe physical memory regions Samuel Holland
2025-10-09 12:37 ` Rob Herring (Arm)
2025-10-09 1:57 ` [PATCH v2 16/18] riscv: mm: Use physical memory aliases to apply PMAs Samuel Holland
2025-10-10 15:06 ` Emil Renner Berthing
2025-10-10 16:12 ` Samuel Holland
2025-10-10 17:04 ` Emil Renner Berthing
2025-10-10 18:01 ` Samuel Holland
2025-10-10 19:55 ` Emil Renner Berthing
2025-10-09 1:57 ` [PATCH v2 17/18] riscv: dts: starfive: jh7100: Use physical memory ranges for DMA Samuel Holland
2025-10-10 14:19 ` Emil Renner Berthing
2025-10-10 16:51 ` Samuel Holland
2025-10-14 9:14 ` Conor Dooley
2025-10-09 1:57 ` [PATCH v2 18/18] riscv: dts: eswin: eic7700: " Samuel Holland
2025-10-10 1:15 ` [PATCH v2 00/18] riscv: Memory type control for platforms with physical memory aliases Andrew Morton
2025-10-10 17:17 ` Samuel Holland
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