From: Samuel Holland <samuel.holland@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <pjw@kernel.org>,
linux-riscv@lists.infradead.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, Conor Dooley <conor@kernel.org>,
Alexandre Ghiti <alex@ghiti.fr>,
Emil Renner Berthing <kernel@esmil.dk>,
Andrew Morton <akpm@linux-foundation.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>
Subject: [PATCH v2 10/18] riscv: ptdump: Only show N and MT bits when enabled in the kernel
Date: Wed, 8 Oct 2025 18:57:46 -0700 [thread overview]
Message-ID: <20251009015839.3460231-11-samuel.holland@sifive.com> (raw)
In-Reply-To: <20251009015839.3460231-1-samuel.holland@sifive.com>
When the Svnapot or Svpbmt extension is not implemented, the
corresponding page table bits are reserved, and must be zero. There is
no need to show them in the ptdump output.
When the Kconfig option for an extension is disabled, we assume it is
not implemented. In that case, the kernel may provide a fallback
definition for the fields, like how _PAGE_MTMASK is defined on riscv32.
Using those fallback definitions in ptdump would produce incorrect
results. To avoid this, hide the fields from the ptdump output.
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
(no changes since v1)
arch/riscv/mm/ptdump.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 3b51690cc8760..6608162459ae0 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -134,11 +134,13 @@ struct prot_bits {
static const struct prot_bits pte_bits[] = {
{
-#ifdef CONFIG_64BIT
+#ifdef CONFIG_RISCV_ISA_SVNAPOT
.mask = _PAGE_NAPOT,
.set = "N",
.clear = ".",
}, {
+#endif
+#ifdef CONFIG_RISCV_ISA_SVPBMT
.mask = _PAGE_MTMASK_SVPBMT,
.set = "MT(%s)",
.clear = " .. ",
@@ -214,7 +216,7 @@ static void dump_prot(struct pg_state *st)
if (val) {
if (pte_bits[i].mask == _PAGE_SOFT)
sprintf(s, pte_bits[i].set, val >> 8);
-#ifdef CONFIG_64BIT
+#ifdef CONFIG_RISCV_ISA_SVPBMT
else if (pte_bits[i].mask == _PAGE_MTMASK_SVPBMT) {
if (val == _PAGE_NOCACHE_SVPBMT)
sprintf(s, pte_bits[i].set, "NC");
--
2.47.2
next prev parent reply other threads:[~2025-10-09 1:59 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-09 1:57 [PATCH v2 00/18] riscv: Memory type control for platforms with physical memory aliases Samuel Holland
2025-10-09 1:57 ` [PATCH v2 01/18] mm/ptdump: Replace READ_ONCE() with standard page table accessors Samuel Holland
2025-10-09 9:34 ` David Hildenbrand
2025-10-09 1:57 ` [PATCH v2 02/18] perf/core: " Samuel Holland
2025-10-09 2:03 ` Anshuman Khandual
2025-10-09 1:57 ` [PATCH v2 03/18] mm: Move the fallback definitions of pXXp_get() Samuel Holland
2025-10-09 1:57 ` [PATCH v2 04/18] mm: Always use page table accessor functions Samuel Holland
2025-10-09 2:10 ` Anshuman Khandual
2025-10-09 1:57 ` [PATCH v2 05/18] mm: Allow page table accessors to be non-idempotent Samuel Holland
2025-10-09 1:57 ` [PATCH v2 06/18] riscv: hibernate: Replace open-coded pXXp_get() Samuel Holland
2025-10-09 1:57 ` [PATCH v2 07/18] riscv: mm: Always use page table accessor functions Samuel Holland
2025-10-09 1:57 ` [PATCH v2 08/18] riscv: mm: Simplify set_p4d() and set_pgd() Samuel Holland
2025-10-09 1:57 ` [PATCH v2 09/18] riscv: mm: Deduplicate _PAGE_CHG_MASK definition Samuel Holland
2025-10-09 1:57 ` Samuel Holland [this message]
2025-10-09 1:57 ` [PATCH v2 11/18] riscv: mm: Fix up memory types when writing page tables Samuel Holland
2025-10-09 1:57 ` [PATCH v2 12/18] riscv: mm: Expose all page table bits to assembly code Samuel Holland
2025-10-09 1:57 ` [PATCH v2 13/18] riscv: alternative: Add an ALTERNATIVE_3 macro Samuel Holland
2025-10-09 1:57 ` [PATCH v2 14/18] riscv: alternative: Allow calls with alternate link registers Samuel Holland
2025-10-09 1:57 ` [PATCH v2 15/18] dt-bindings: riscv: Describe physical memory regions Samuel Holland
2025-10-09 12:37 ` Rob Herring (Arm)
2025-10-09 1:57 ` [PATCH v2 16/18] riscv: mm: Use physical memory aliases to apply PMAs Samuel Holland
2025-10-10 15:06 ` Emil Renner Berthing
2025-10-10 16:12 ` Samuel Holland
2025-10-10 17:04 ` Emil Renner Berthing
2025-10-10 18:01 ` Samuel Holland
2025-10-10 19:55 ` Emil Renner Berthing
2025-10-09 1:57 ` [PATCH v2 17/18] riscv: dts: starfive: jh7100: Use physical memory ranges for DMA Samuel Holland
2025-10-10 14:19 ` Emil Renner Berthing
2025-10-10 16:51 ` Samuel Holland
2025-10-14 9:14 ` Conor Dooley
2025-10-09 1:57 ` [PATCH v2 18/18] riscv: dts: eswin: eic7700: " Samuel Holland
2025-10-10 1:15 ` [PATCH v2 00/18] riscv: Memory type control for platforms with physical memory aliases Andrew Morton
2025-10-10 17:17 ` Samuel Holland
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