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Enable DCBM offload: echo 1 > /sys/kernel/dcbm/offloading echo NR_DMA_CHAN_TO_USE > /sys/kernel/dcbm/nr_dma_chan Disable DCBM offload: echo 0 > /sys/kernel/dcbm/offloading Signed-off-by: Shivank Garg --- drivers/migoffcopy/Kconfig | 8 + drivers/migoffcopy/Makefile | 1 + drivers/migoffcopy/dcbm/Makefile | 1 + drivers/migoffcopy/dcbm/dcbm.c | 415 +++++++++++++++++++++++++++++++ 4 files changed, 425 insertions(+) create mode 100644 drivers/migoffcopy/dcbm/Makefile create mode 100644 drivers/migoffcopy/dcbm/dcbm.c diff --git a/drivers/migoffcopy/Kconfig b/drivers/migoffcopy/Kconfig index e73698af3e72..c1b2eff7650d 100644 --- a/drivers/migoffcopy/Kconfig +++ b/drivers/migoffcopy/Kconfig @@ -6,4 +6,12 @@ config MTCOPY_CPU Interface MT COPY CPU driver for batch page migration offloading. Say Y if you want to try offloading with MultiThreaded CPU copy APIs. +config DCBM_DMA + bool "DMA Core Batch Migrator" + depends on OFFC_MIGRATION && DMA_ENGINE + default n + help + Interface DMA driver for batch page migration offloading. + Say Y if you want to try offloading with DMAEngine APIs + based driver. diff --git a/drivers/migoffcopy/Makefile b/drivers/migoffcopy/Makefile index 0a3c356d67e6..dedc86ff54c1 100644 --- a/drivers/migoffcopy/Makefile +++ b/drivers/migoffcopy/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_MTCOPY_CPU) += mtcopy/ +obj-$(CONFIG_DCBM_DMA) += dcbm/ diff --git a/drivers/migoffcopy/dcbm/Makefile b/drivers/migoffcopy/dcbm/Makefile new file mode 100644 index 000000000000..56ba47cce0f1 --- /dev/null +++ b/drivers/migoffcopy/dcbm/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_DCBM_DMA) += dcbm.o diff --git a/drivers/migoffcopy/dcbm/dcbm.c b/drivers/migoffcopy/dcbm/dcbm.c new file mode 100644 index 000000000000..87a58c0c3b9b --- /dev/null +++ b/drivers/migoffcopy/dcbm/dcbm.c @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * + * DMA batch-offloading interface driver + * + * Copyright (C) 2024-25 Advanced Micro Devices, Inc. + */ + +#include +#include +#include +#include +#include + +#define MAX_DMA_CHANNELS 16 + +static bool offloading_enabled; +static unsigned int nr_dma_channels = 1; +static DEFINE_MUTEX(dcbm_mutex); + +struct dma_work { + struct dma_chan *chan; + struct completion done; + atomic_t pending; + struct sg_table *src_sgt; + struct sg_table *dst_sgt; + bool mapped; +}; + +static void dma_completion_callback(void *data) +{ + struct dma_work *work = data; + + if (atomic_dec_and_test(&work->pending)) + complete(&work->done); +} + +static int setup_sg_tables(struct dma_work *work, struct list_head **src_pos, + struct list_head **dst_pos, int nr) +{ + struct scatterlist *sg_src, *sg_dst; + struct device *dev; + int i, ret; + + work->src_sgt = kmalloc(sizeof(*work->src_sgt), GFP_KERNEL); + if (!work->src_sgt) + return -ENOMEM; + work->dst_sgt = kmalloc(sizeof(*work->dst_sgt), GFP_KERNEL); + if (!work->dst_sgt) + goto err_free_src; + + ret = sg_alloc_table(work->src_sgt, nr, GFP_KERNEL); + if (ret) + goto err_free_dst; + ret = sg_alloc_table(work->dst_sgt, nr, GFP_KERNEL); + if (ret) + goto err_free_src_table; + + sg_src = work->src_sgt->sgl; + sg_dst = work->dst_sgt->sgl; + for (i = 0; i < nr; i++) { + struct folio *src = list_entry(*src_pos, struct folio, lru); + struct folio *dst = list_entry(*dst_pos, struct folio, lru); + + sg_set_folio(sg_src, src, folio_size(src), 0); + sg_set_folio(sg_dst, dst, folio_size(dst), 0); + + *src_pos = (*src_pos)->next; + *dst_pos = (*dst_pos)->next; + + if (i < nr - 1) { + sg_src = sg_next(sg_src); + sg_dst = sg_next(sg_dst); + } + } + + dev = dmaengine_get_dma_device(work->chan); + if (!dev) { + ret = -ENODEV; + goto err_free_dst_table; + } + ret = dma_map_sgtable(dev, work->src_sgt, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_NO_KERNEL_MAPPING); + if (ret) + goto err_free_dst_table; + ret = dma_map_sgtable(dev, work->dst_sgt, DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_NO_KERNEL_MAPPING); + if (ret) + goto err_unmap_src; + /* Verify mapping produced same number of entries */ + if (work->src_sgt->nents != work->dst_sgt->nents) { + pr_err("Mismatched SG entries after mapping: src=%d dst=%d\n", + work->src_sgt->nents, work->dst_sgt->nents); + ret = -EINVAL; + goto err_unmap_dst; + } + work->mapped = true; + return 0; + +err_unmap_dst: + dma_unmap_sgtable(dev, work->dst_sgt, DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_NO_KERNEL_MAPPING); +err_unmap_src: + dma_unmap_sgtable(dev, work->src_sgt, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_NO_KERNEL_MAPPING); +err_free_dst_table: + sg_free_table(work->dst_sgt); +err_free_src_table: + sg_free_table(work->src_sgt); +err_free_dst: + kfree(work->dst_sgt); + work->dst_sgt = NULL; +err_free_src: + kfree(work->src_sgt); + work->src_sgt = NULL; + pr_err("DCBM: Failed to setup SG tables\n"); + return ret; +} + +static void cleanup_dma_work(struct dma_work *works, int actual_channels) +{ + struct device *dev; + int i; + + if (!works) + return; + + for (i = 0; i < actual_channels; i++) { + if (!works[i].chan) + continue; + + dev = dmaengine_get_dma_device(works[i].chan); + + /* Terminate any pending transfers */ + if (atomic_read(&works[i].pending) > 0) + dmaengine_terminate_sync(works[i].chan); + + if (dev && works[i].mapped) { + if (works[i].src_sgt) { + dma_unmap_sgtable(dev, works[i].src_sgt, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_NO_KERNEL_MAPPING); + sg_free_table(works[i].src_sgt); + kfree(works[i].src_sgt); + } + if (works[i].dst_sgt) { + dma_unmap_sgtable(dev, works[i].dst_sgt, DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_NO_KERNEL_MAPPING); + sg_free_table(works[i].dst_sgt); + kfree(works[i].dst_sgt); + } + } + dma_release_channel(works[i].chan); + } + kfree(works); +} + +static int submit_dma_transfers(struct dma_work *work) +{ + struct scatterlist *sg_src, *sg_dst; + struct dma_async_tx_descriptor *tx; + unsigned long flags = DMA_CTRL_ACK; + dma_cookie_t cookie; + int i; + + /* Logic: send single callback for the entire batch */ + atomic_set(&work->pending, 1); + + sg_src = work->src_sgt->sgl; + sg_dst = work->dst_sgt->sgl; + /* Iterate over DMA-mapped entries */ + for_each_sgtable_dma_sg(work->src_sgt, sg_src, i) { + /* Only interrupt on the last transfer */ + if (i == work->src_sgt->nents - 1) + flags |= DMA_PREP_INTERRUPT; + + tx = dmaengine_prep_dma_memcpy(work->chan, + sg_dma_address(sg_dst), + sg_dma_address(sg_src), + sg_dma_len(sg_src), + flags); + if (!tx) { + atomic_set(&work->pending, 0); + return -EIO; + } + + /* Only set callback on last transfer */ + if (i == work->src_sgt->nents - 1) { + tx->callback = dma_completion_callback; + tx->callback_param = work; + } + + cookie = dmaengine_submit(tx); + if (dma_submit_error(cookie)) { + atomic_set(&work->pending, 0); + return -EIO; + } + sg_dst = sg_next(sg_dst); + } + return 0; +} + +/** + * folios_copy_dma - Copy folios using DMA engine + * @dst_list: Destination folio list + * @src_list: Source folio list + * @nr_folios: Number of folios to copy + * + * Return: 0. Fallback to CPU copy on any error. + */ +static int folios_copy_dma(struct list_head *dst_list, + struct list_head *src_list, + unsigned int nr_folios) +{ + struct dma_work *works; + struct list_head *src_pos = src_list->next; + struct list_head *dst_pos = dst_list->next; + int i, folios_per_chan, ret = 0; + dma_cap_mask_t mask; + int actual_channels = 0; + int max_channels; + + max_channels = min3(nr_dma_channels, nr_folios, MAX_DMA_CHANNELS); + + works = kcalloc(max_channels, sizeof(*works), GFP_KERNEL); + if (!works) + goto fallback; + + dma_cap_zero(mask); + dma_cap_set(DMA_MEMCPY, mask); + + for (i = 0; i < max_channels; i++) { + works[actual_channels].chan = dma_request_chan_by_mask(&mask); + if (IS_ERR(works[actual_channels].chan)) + break; + init_completion(&works[actual_channels].done); + actual_channels++; + } + + if (actual_channels == 0) { + kfree(works); + goto fallback; + } + + for (i = 0; i < actual_channels; i++) { + folios_per_chan = nr_folios * (i + 1) / actual_channels - + (nr_folios * i) / actual_channels; + if (folios_per_chan == 0) + continue; + + ret = setup_sg_tables(&works[i], &src_pos, &dst_pos, folios_per_chan); + if (ret) + goto cleanup; + } + + for (i = 0; i < actual_channels; i++) { + ret = submit_dma_transfers(&works[i]); + if (ret) { + dev_err(dmaengine_get_dma_device(works[i].chan), + "Failed to submit transfers for channel %d\n", i); + goto cleanup; + } + } + + for (i = 0; i < actual_channels; i++) { + if (atomic_read(&works[i].pending) > 0) + dma_async_issue_pending(works[i].chan); + } + + for (i = 0; i < actual_channels; i++) { + if (atomic_read(&works[i].pending) > 0) { + if (!wait_for_completion_timeout(&works[i].done, msecs_to_jiffies(10000))) { + dev_err(dmaengine_get_dma_device(works[i].chan), + "DMA timeout on channel %d\n", i); + ret = -ETIMEDOUT; + goto cleanup; + } + } + } + +cleanup: + cleanup_dma_work(works, actual_channels); + if (ret) + goto fallback; + return 0; +fallback: + /* Fall back to CPU copy */ + pr_err("DCBM: Falling back to CPU copy\n"); + folios_mc_copy(dst_list, src_list, nr_folios); + return 0; +} + +static struct migrator dma_migrator = { + .name = "DCBM", + .migrate_offc = folios_copy_dma, + .owner = THIS_MODULE, +}; + +static ssize_t offloading_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%d\n", offloading_enabled); +} + +static ssize_t offloading_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + bool enable; + int ret; + + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + mutex_lock(&dcbm_mutex); + + if (enable == offloading_enabled) { + pr_err("migration offloading is already %s\n", + enable ? "ON" : "OFF"); + goto out; + } + + if (enable) { + start_offloading(&dma_migrator); + offloading_enabled = true; + pr_info("migration offloading is now ON\n"); + } else { + stop_offloading(); + offloading_enabled = false; + pr_info("migration offloading is now OFF\n"); + } +out: + mutex_unlock(&dcbm_mutex); + return count; +} + +static ssize_t nr_dma_chan_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", nr_dma_channels); +} + +static ssize_t nr_dma_chan_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + unsigned int val; + int ret; + + ret = kstrtouint(buf, 0, &val); + if (ret) + return ret; + + if (val < 1 || val > MAX_DMA_CHANNELS) + return -EINVAL; + + mutex_lock(&dcbm_mutex); + nr_dma_channels = val; + mutex_unlock(&dcbm_mutex); + + return count; +} + +static struct kobj_attribute offloading_attr = __ATTR_RW(offloading); +static struct kobj_attribute nr_dma_chan_attr = __ATTR_RW(nr_dma_chan); + +static struct attribute *dcbm_attrs[] = { + &offloading_attr.attr, + &nr_dma_chan_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(dcbm); + +static struct kobject *dcbm_kobj; + +static int __init dcbm_init(void) +{ + int ret; + + dcbm_kobj = kobject_create_and_add("dcbm", kernel_kobj); + if (!dcbm_kobj) + return -ENOMEM; + + ret = sysfs_create_groups(dcbm_kobj, dcbm_groups); + if (ret) { + kobject_put(dcbm_kobj); + return ret; + } + + pr_info("DMA Core Batch Migrator initialized\n"); + return 0; +} + +static void __exit dcbm_exit(void) +{ + /* Ensure offloading is stopped before module unload */ + mutex_lock(&dcbm_mutex); + if (offloading_enabled) { + stop_offloading(); + offloading_enabled = false; + } + mutex_unlock(&dcbm_mutex); + + sysfs_remove_groups(dcbm_kobj, dcbm_groups); + kobject_put(dcbm_kobj); + + pr_info("DMA Core Batch Migrator unloaded\n"); +} + +module_init(dcbm_init); +module_exit(dcbm_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Shivank Garg"); +MODULE_DESCRIPTION("DMA Core Batch Migrator"); -- 2.43.0