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Tue, 09 Sep 2025 10:13:00 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-5104c5a4d0dsm5507495173.0.2025.09.09.10.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Sep 2025 10:13:00 -0700 (PDT) Date: Tue, 9 Sep 2025 12:12:59 -0500 From: Andrew Jones To: Chunyan Zhang Cc: linux-riscv@lists.infradead.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Deepak Gupta , Ved Shanbhogue , Alexander Viro , Christian Brauner , Jan Kara , Andrew Morton , Peter Xu , Arnd Bergmann , David Hildenbrand , Lorenzo Stoakes , "Liam R . Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Axel Rasmussen , Yuanchu Xie , Chunyan Zhang Subject: Re: [PATCH V10 3/5] riscv: Add RISC-V Svrsw60t59b extension support Message-ID: <20250909-2130daabd7f57a8a357c677f@orel> References: <20250909095611.803898-1-zhangchunyan@iscas.ac.cn> <20250909095611.803898-4-zhangchunyan@iscas.ac.cn> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250909095611.803898-4-zhangchunyan@iscas.ac.cn> X-Rspamd-Queue-Id: 5889D180008 X-Stat-Signature: wit99tjoi99j16tdh7drtga68jafg53b X-Rspam-User: X-Rspamd-Server: rspam09 X-HE-Tag: 1757437985-819873 X-HE-Meta: U2FsdGVkX1/ZfeEsjr2alT9fliF+o+61aGucDwbSEvgeb2Q0cFqXtnhKmmKk/p6LDZwayIx59ZiLbyF1W8aAta98kImlsrV8aBMwx314k0JK6e1+ylrsE4IBsuH09AeLSBaB+22qNLvYI6ciL4HXiZmmV+HxBh3eGGk1cYfxsHZsRno+XmNQ+dh1nsvXcVOOr9S9NVVKmTbjdRNGCzkafCEp2AeDS1GvHOk5tCgBo0QTNX+gvB9Xmjfdqd6qRo/QQ/eAADAhkR/JvQ2IIkcKqWOJ6FbPqP1Apl/sknB9DiN8Us5fSE011Nd4uhn6li7CbisyoXOcAQgyjirs+hspbvpLAE2DamMSUG19JzyKMtqArTj39h1vxCSoZehHIYe0Xt3fyoplMiyoFqJKHbEowUjyISKl3ROV6z9OHo9+AsY+ummATffYm46oUhtvsDPYDtF+UyRubGZmO3ar5bDskEHjqebylZ2HPqQ9/HukMr9WSxM4gyQvuE9ErfhM89v7UIDa3qx6eWdy8AeH2kkvvgU4jfOJglEkTAp95d/ocM5yrsUYpooaHdN1c3/X+wKsiP2QgYbz3Mp+/Si0zYx9L9FASk1bNlmNEDBandBeMMoT0mB8/nyzN68J1lgkp1/otcqjtJ+TXGH8ZvtyvsjATBUfgIlBS/W2JvoEKl9769VJz4mqpTuCX7B/6JKj4Hc6r08k9MdMSErXxdO84XyXFhK0cLcBUUKWRWmyRLsGTRYv5gnPpF7wo2s9oKz7sN+cVKb/kwX0aUYFRZfU+FAY7dayyG9O3ghdcJzVPrIInNOh8PkWj562UlmJGVy/Jkgo2DXkuy9/IlMSWfyik6wNeT4C7ldNFjVmin7RV48VCynlXaJjxQkNNcnRp6KgXJpxNc+ZpyLg0DSpa0DWOcCbUTkjodhuz7igHuSDff8Kfp+ZeMLHZTsiQY8Wzr/jL5UGDUYWYUXxEkIHbeZmpbA fXnX6etS e1ZR4IUzev5JNmZTJlliO2Zaycnfwct7PTJOgoZesXgJz6HBt1+4hlVxrBNa80Q/BN0SOpMqBNbAgNaVxbdpY0Jx+BrpeAPkCAsPcWGQCGqKsVkuohJtbuh8rYQ9Snj7lP2Ij+Tquu5V0bwSSXuHFkh9zPUqe+hb5hdFiepR+p31WZmUTklXfzGk6ePdZTzsQmXqVKIRUQKv8h1JpW1abcm1qZJV+ytvTLxLuoYMyzZhh0RK2EjTrspSikRNxRlD3Dcj9nNtsps8mvibnshSlgjxCWkInpUAfxZ8IQ8p+x16lc6PLFtZYoRk2T6QgdnhGxPGX1KhkB2JdmNYdhWtTTkKQOKw4beFtYu+o/2MMzTJGUTlXT/44kboCtdOf4avrO+7YVMC5ET/l80o5mD9cvoFAIOdNABa3JFj9y0uXx1FKcncZ2CavrG3YRFiITf5rQUspe6LiM5QgcTT+UjPor0EiPqTZJeYDoe0oaQsEK9UP44z9tqrBt8FdBa8MX8X9JaKVo2Bo2OFKrqf5g/zSU1UeCMP1mheDLvl2JnTx0zmcNaljZNYYwQCN9AxotH6Nnojy9OsOEVj/lIfaUdYZVMdl/R2vsNA1cET1Dhx1MBzJSFKkW48bOUHXbYCTnhvRqPX15IG3jEdnHq4TiBLwg85uJRJJh9W7M/ix X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Tue, Sep 09, 2025 at 05:56:09PM +0800, Chunyan Zhang wrote: > The Svrsw60t59b extension allows to free the PTE reserved bits 60 > and 59 for software to use. > > Reviewed-by: Alexandre Ghiti > Signed-off-by: Chunyan Zhang > --- > arch/riscv/Kconfig | 14 ++++++++++++++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 3 files changed, 16 insertions(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index a4b233a0659e..d99df67cc7a4 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -862,6 +862,20 @@ config RISCV_ISA_ZICBOP > > If you don't know what to do here, say Y. > > +config RISCV_ISA_SVRSW60T59B > + bool "Svrsw60t59b extension support for using PTE bits 60 and 59" > + depends on MMU && 64BIT > + depends on RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Svrsw60t59b > + extension and enable its usage. > + > + The Svrsw60t59b extension allows to free the PTE reserved bits 60 > + and 59 for software to use. > + > + If you don't know what to do here, say Y. > + > config TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI > def_bool y > # https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index affd63e11b0a..f98fcb5c17d5 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -106,6 +106,7 @@ > #define RISCV_ISA_EXT_ZAAMO 97 > #define RISCV_ISA_EXT_ZALRSC 98 > #define RISCV_ISA_EXT_ZICBOP 99 > +#define RISCV_ISA_EXT_SVRSW60T59B 100 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 743d53415572..de29562096ff 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -540,6 +540,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), > __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), > __RISCV_ISA_EXT_DATA(svvptc, RISCV_ISA_EXT_SVVPTC), > + __RISCV_ISA_EXT_DATA(svrsw60t59b, RISCV_ISA_EXT_SVRSW60T59B), svrsw60t59b should come before svvptc. See the ordering rule comment at the top of the array. Otherwise, Reviewed-by: Andrew Jones > }; > > const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); > -- > 2.34.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv