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[108.26.215.125]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b2b8e6023asm3121361cf.53.2025.08.22.10.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 10:47:33 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Oleg Nesterov , Kees Cook , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang Kan" , Shuah Khan , Jesse Taube , Himanshu Chauhan , Charlie Jenkins , Samuel Holland , Conor Dooley , Deepak Gupta , Andrew Jones , Atish Patra , Anup Patel , Mayuresh Chitale , Evan Green , WangYuli , Huacai Chen , Arnd Bergmann , Andrew Morton , Luis Chamberlain , "Mike Rapoport (Microsoft)" , Nam Cao , Yunhui Cui , Joel Granados , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Sebastian Andrzej Siewior , Celeste Liu , Chunyan Zhang , Nylon Chen , Thomas Gleixner , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , Vincenzo Frascino , Joey Gouly , Ravi Bangoria , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Joel Stanley Subject: [PATCH 7/8] riscv: ptrace: Add hw breakpoint regset Date: Fri, 22 Aug 2025 10:47:14 -0700 Message-ID: <20250822174715.1269138-8-jesse@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250822174715.1269138-1-jesse@rivosinc.com> References: <20250822174715.1269138-1-jesse@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam10 X-Rspamd-Queue-Id: D8048140009 X-Stat-Signature: 1jocphmyzg6fziiif9yre91xdwchn7j9 X-Rspam-User: X-HE-Tag: 1755884854-778955 X-HE-Meta: U2FsdGVkX18KUI20XFHHIWC+FpPQzayZWO2mrtoGkKQJieMLQ+c0TJWk5ds73UvJMx1S4GTHyTEPRjOSR4IWkOZuih9k2n+d18EkyOkAfK5izdetXAxp7fTrqWd9FcKJpn2veSHh5EO/Zn3F3rSA6iE7MVsoMWAIJHYwOSOG4fLwdF7fOz5jaeMfwn/5h4pX6nShvRlllwkizRVQXP8pkQKS1ytI/7RY4FM6EcoDYc7YdTZptd1CsqVRXCZLEuBK+wvRSF28j3bikEMDY7GfMzQ1ZAvSA2i4e46W6uyBfBEnqKqH8W8k3pmdijN9dVc0DY4//2YrEYxsBQtoORibbYC+cSpdP+g8NMnd9oXUdwTG2isiUsS1wbf+cefHrpT7KoLtXlrJRWqGgXeIJgfIGskmSG+HyOl2pyuuJx1mLPvZ0kg6Ss0DXxnxBWxRg2NixRbVEOo46qRlEjUG2suQdfBnOdfbA9DMEj6P4w4OddabOlAxV5gpgE9tkUhyubQEO2hEmSryycX/MsfA/7ZxVcW9cH+9dTFR40UYWBsKH9Tkzm3jknpJB5XkcQpJfHMMx1B6/O2IfmQvTzMZ+8IlighaXglJYqWXaYJBSqrfg1Xas76wKC/wLJQJ9VfCd605mqvo3wpD7cZMm+zM7HLx8i/8cR6F03VgixiZTTnQT3Rqm8zpuE6phKC1MsEiWJQde5jqGAqeaN4Oa2xJTVd3HOuZWS+zaXtHE/YqJbzohLmBdXtQG4siEs7MHxEcByaFIzMA5GPuPsMfeoYVMhXq0RNqVCYdxJ8aYanjQ4jMUpmvykScxia6PicOIkznPSQqAQ+bS1Apr6Xvvd14Y/uaigwIzrVcKA+oy1jgVpYE+SyDekFZa4KOCfUk6DQ3vQAuzFYPL0y0gkygtf7nYwJXedpe+lUFCL9q+tFjz19WExQWQ6l1SVgSfDx9Qrmshva7SQlmDty98lkZwdKvqt0 +ZlEhjek chzVGsoi0GrIBn+Um1OBcFvVOhDPdeqrRbGyOI97PEDmDJnsB2sl1p0RlVG9XjXXcs6me7xnSnbCQykzVyjT9lE1fKND9gxAw3Qz9VNdlj0QweRZKShWbmjnMypR9ipkMi9OacbX4N15oa3vr1ziTjCrnnz+vvzYlkyEenuNFpkoRhKQS1iSfvMOfljdueZ0TubWU+39IG7OSpOudb6uM/BNKMAfcAGEmwJSCleRJFaBnuegZDEzj7+M2i/7egapIxYTyb0oWncPMdaOiMRDgISJPrA09G+cRS64cJ2E8VvOYc4WExdbs96eAUpo1lh4QA/wId2+Jwue7+44= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Add ability to setup hw breakpoints using REGSET use the __riscv_hwdebug_state structure to configure breakpoints. Signed-off-by: Jesse Taube --- RFC -> V1: - New commit V1 -> V2: - No change --- arch/riscv/kernel/ptrace.c | 59 ++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 2 ++ tools/include/uapi/linux/elf.h | 1 + 3 files changed, 62 insertions(+) diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index e097e6a61910..fbd0097ec168 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -33,6 +33,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_SUPM REGSET_TAGGED_ADDR_CTRL, #endif +#ifdef CONFIG_HAVE_HW_BREAKPOINT + REGSET_HW_BREAK +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -280,7 +283,53 @@ static long ptrace_sethbpregs(struct task_struct *child, unsigned long idx, return -EFAULT; return ptrace_hbp_set(child, idx, &state); +} +static int hw_break_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + struct __riscv_hwdebug_state state; + int ret, idx, offset, limit; + + idx = offset = 0; + limit = regset->n * regset->size; + while (count && offset < limit) { + if (count < sizeof(state)) + return -EINVAL; + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &state, + offset, offset + sizeof(state)); + if (ret) + return ret; + ret = ptrace_hbp_set(target, idx, &state); + if (ret) + return ret; + offset += sizeof(state); + idx++; + } + + return 0; +} + +static int hw_break_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + int ret, idx = 0; + struct __riscv_hwdebug_state state; + + while (to.left) { + ret = ptrace_hbp_get(target, idx, &state); + if (ret) + return ret; + + membuf_write(&to, &state, sizeof(state)); + idx++; + } + + return 0; } #endif @@ -324,6 +373,16 @@ static const struct user_regset riscv_user_regset[] = { .set = tagged_addr_ctrl_set, }, #endif +#ifdef CONFIG_HAVE_HW_BREAKPOINT + [REGSET_HW_BREAK] = { + .core_note_type = NT_RISCV_HW_BREAK, + .n = sizeof(struct __riscv_hwdebug_state) / sizeof(unsigned long), + .size = sizeof(unsigned long), + .align = sizeof(unsigned long), + .regset_get = hw_break_get, + .set = hw_break_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 819ded2d39de..7a32073e0d68 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -545,6 +545,8 @@ typedef struct elf64_shdr { #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NN_RISCV_TAGGED_ADDR_CTRL "LINUX" #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ +#define NN_RISCV_HW_BREAK "LINUX" +#define NT_RISCV_HW_BREAK 0x903 /* RISC-V hardware breakpoint registers */ #define NN_LOONGARCH_CPUCFG "LINUX" #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NN_LOONGARCH_CSR "LINUX" diff --git a/tools/include/uapi/linux/elf.h b/tools/include/uapi/linux/elf.h index 5834b83d7f9a..b5f35df1de7a 100644 --- a/tools/include/uapi/linux/elf.h +++ b/tools/include/uapi/linux/elf.h @@ -460,6 +460,7 @@ typedef struct elf64_shdr { #define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */ #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ +#define NT_RISCV_HW_BREAK 0x903 /* RISC-V hardware breakpoint registers */ #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */ #define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */ -- 2.43.0