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[108.26.215.125]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4b2b8e6023asm3121361cf.53.2025.08.22.10.47.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 10:47:17 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Oleg Nesterov , Kees Cook , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang Kan" , Shuah Khan , Jesse Taube , Himanshu Chauhan , Charlie Jenkins , Samuel Holland , Conor Dooley , Deepak Gupta , Andrew Jones , Atish Patra , Anup Patel , Mayuresh Chitale , Evan Green , WangYuli , Huacai Chen , Arnd Bergmann , Andrew Morton , Luis Chamberlain , "Mike Rapoport (Microsoft)" , Nam Cao , Yunhui Cui , Joel Granados , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Sebastian Andrzej Siewior , Celeste Liu , Chunyan Zhang , Nylon Chen , Thomas Gleixner , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , Vincenzo Frascino , Joey Gouly , Ravi Bangoria , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Joel Stanley Subject: [PATCH 0/8] riscv: add initial support for hardware breakpoints Date: Fri, 22 Aug 2025 10:47:07 -0700 Message-ID: <20250822174715.1269138-1-jesse@rivosinc.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: 1A9EC40008 X-Stat-Signature: ejtf469aa9utrbg5faky88indkhx4je3 X-Rspam-User: X-HE-Tag: 1755884838-283572 X-HE-Meta: U2FsdGVkX19R9dMiSpd07S/k8JtvfNDnE7QIXcPJ+XBydi57bjb2+Byz96P7CS/8w7d3GgIFh2YdGH/tAck219HQqR6iPutImNXw7Dx9gYM2TxTaz1wptvT7cOyKW0y7OZF8DJoCPybtzA6uhoEOAzpHAqx8pkztNO5KXKvQ+yIDnKa5s9xIiuEbzbCu7j3togjrk1OoCbfsyQs2Z0M7dxzPKZ0CkrkqlNBQSqZcL4RCOaSeK3Rem1otVU8PQgni8NA+jdvQO/hj/hTykTgDb/qwQdrt0AgGB99rcUYQFTd8gKX5wsZxFl0Mp8nbs4zpZTVMsDjt31IWxTM+GrTeIJcouT8Ju7JRYAYqeLMAObNCw7rMF2Hj4b64RtmwotVmQaleuJ8q009HXQ9DS+C2HXMkDWi8jcHtS11OS/wFy3TRZZAc5g5QIyfeLBXUJKHNvKJ3Lk1rhrm8nG2F6zXK5ShltSw1k7CT+/F5aoU8WDG+H9amfXH5HR+YueGJAqZoWCCUyNPFx/dA3L1rGDVfBx9nQAW42317RoE8hPETuCF58UMzHAaNsK7JOVDnVDRZOtbouyah01/cwzKoXn2zHgaYAhEoC1gdFBOeQ3OjTmKSVG0/ny2Y+ctVMqDWX6CJ4QGytj9XDXbRHDpFcDWQ0G8DJJTZ3EBzoTTGgnQgB/kWYYuuNm5bP8nHVmxg9jtSZSGqUbp16qHz4Ff2/EkMV4un7L6K/i95viIdAxuN7jUbYwXAJGNSIxgC2FmGF7K8PfsjxjQH7R7zFyebcsMwHbqB8wjix3pIaokiDpo0uLQeamMcVEI5vOCpTbwWYN6Ik39JXwtC9UQK04f1SKQ/MqESGYts0MCwgQSn5GBB5JDwmv6RmD0/7NFIeXPHj6ey2EnPJJkc/+FVZ+zYS9X4bhyzK4BaG9QC+REaaCcJofiPrMEDL9NEhqj2Ouyddxv1VAX5/cJ66xQKhrf7Sxo VJUKZ0gv 8AhmJbcsrIZfvYbkZVGT2N7UJrA== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patchset adds initial support for hardware breakpoints and watchpoints to the RISC-V architecture. The framework is built on top of perf subsystem and SBI debug trigger extension. Currently following features are not supported and are in works: - icount for single stepping - Virtualization of debug triggers - kernel space debug triggers The SBI debug trigger extension can be found at: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-debug-triggers.adoc The Sdtrig ISA is part of RISC-V debug specification which can be found at: https://github.com/riscv/riscv-debug-spec based off the original RFC by Himanshu Chauhan here: https://lore.kernel.org/lkml/20240222125059.13331-1-hchauhan@ventanamicro.com/ Second RFC by Jesse Taube here: https://lore.kernel.org/lkml/20250722173829.984082-1-jesse@rivosinc.com/ Himanshu Chauhan (2): riscv: Add SBI debug trigger extension and function ids riscv: Introduce support for hardware break/watchpoints Jesse Taube (6): riscv: Add insn.c, consolidate instruction decoding riscv: insn: Add get_insn_nofault riscv: hw_breakpoint: Use icount for single stepping riscv: ptrace: Add hw breakpoint support riscv: ptrace: Add hw breakpoint regset selftests: riscv: Add test for hardware breakpoints arch/riscv/Kconfig | 2 + arch/riscv/include/asm/bug.h | 12 - arch/riscv/include/asm/hw_breakpoint.h | 59 ++ arch/riscv/include/asm/insn.h | 132 ++- arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/processor.h | 4 + arch/riscv/include/asm/sbi.h | 33 +- arch/riscv/include/uapi/asm/ptrace.h | 9 + arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/hw_breakpoint.c | 763 ++++++++++++++++++ arch/riscv/kernel/insn.c | 165 ++++ arch/riscv/kernel/kgdb.c | 102 +-- arch/riscv/kernel/probes/kprobes.c | 1 + arch/riscv/kernel/process.c | 4 + arch/riscv/kernel/ptrace.c | 169 ++++ arch/riscv/kernel/traps.c | 11 +- arch/riscv/kernel/traps_misaligned.c | 93 +-- include/uapi/linux/elf.h | 2 + tools/include/uapi/linux/elf.h | 1 + tools/perf/tests/tests.h | 3 +- tools/testing/selftests/riscv/Makefile | 2 +- .../selftests/riscv/breakpoints/.gitignore | 1 + .../selftests/riscv/breakpoints/Makefile | 13 + .../riscv/breakpoints/breakpoint_test.c | 246 ++++++ 24 files changed, 1641 insertions(+), 191 deletions(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c create mode 100644 arch/riscv/kernel/insn.c create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c -- 2.43.0