From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: Catalin Marinas <catalin.marinas@arm.com>, <james.morse@arm.com>,
<linux-cxl@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-acpi@vger.kernel.org>, <linux-arch@vger.kernel.org>,
<linux-mm@kvack.org>, Will Deacon <will@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
"H . Peter Anvin" <hpa@zytor.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: Yicong Yang <yangyicong@huawei.com>, <linuxarm@huawei.com>,
Yushan Wang <wangyushan12@huawei.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
<x86@kernel.org>, Andy Lutomirski <luto@kernel.org>
Subject: [PATCH v3 2/8] memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion()
Date: Wed, 20 Aug 2025 11:29:44 +0100 [thread overview]
Message-ID: <20250820102950.175065-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20250820102950.175065-1-Jonathan.Cameron@huawei.com>
From: Yicong Yang <yangyicong@hisilicon.com>
Extend cpu_cache_invalidate_memregion() to support invalidate certain range
of memory by introducing start and length parameters. Control of types of
invalidation is left for when usecases turn up. For now everything is
Clean and Invalidate.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Acked-by: Davidlohr Bueso <dave@stgolabs.net>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
v3: Rebase on top of previous patch that removed the IO_RESDESC_*
parameter.
---
arch/x86/mm/pat/set_memory.c | 2 +-
drivers/cxl/core/region.c | 5 ++++-
drivers/nvdimm/region.c | 2 +-
drivers/nvdimm/region_devs.c | 2 +-
include/linux/memregion.h | 7 +++++--
5 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/x86/mm/pat/set_memory.c b/arch/x86/mm/pat/set_memory.c
index 4019b17fb65e..292c7202faed 100644
--- a/arch/x86/mm/pat/set_memory.c
+++ b/arch/x86/mm/pat/set_memory.c
@@ -368,7 +368,7 @@ bool cpu_cache_has_invalidate_memregion(void)
}
EXPORT_SYMBOL_NS_GPL(cpu_cache_has_invalidate_memregion, "DEVMEM");
-int cpu_cache_invalidate_memregion(void)
+int cpu_cache_invalidate_memregion(phys_addr_t start, size_t len)
{
if (WARN_ON_ONCE(!cpu_cache_has_invalidate_memregion()))
return -ENXIO;
diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
index d7fa76810f82..410e41cef5d3 100644
--- a/drivers/cxl/core/region.c
+++ b/drivers/cxl/core/region.c
@@ -228,7 +228,10 @@ static int cxl_region_invalidate_memregion(struct cxl_region *cxlr)
return -ENXIO;
}
- cpu_cache_invalidate_memregion();
+ if (!cxlr->params.res)
+ return -ENXIO;
+ cpu_cache_invalidate_memregion(cxlr->params.res->start,
+ resource_size(cxlr->params.res));
return 0;
}
diff --git a/drivers/nvdimm/region.c b/drivers/nvdimm/region.c
index c43506448edf..62535d200402 100644
--- a/drivers/nvdimm/region.c
+++ b/drivers/nvdimm/region.c
@@ -110,7 +110,7 @@ static void nd_region_remove(struct device *dev)
* here is ok.
*/
if (cpu_cache_has_invalidate_memregion())
- cpu_cache_invalidate_memregion();
+ cpu_cache_invalidate_memregion(0, -1);
}
static int child_notify(struct device *dev, void *data)
diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c
index 3cdd93d40997..7c1d27c75b73 100644
--- a/drivers/nvdimm/region_devs.c
+++ b/drivers/nvdimm/region_devs.c
@@ -90,7 +90,7 @@ static int nd_region_invalidate_memregion(struct nd_region *nd_region)
}
}
- cpu_cache_invalidate_memregion();
+ cpu_cache_invalidate_memregion(0, -1);
out:
for (i = 0; i < nd_region->ndr_mappings; i++) {
struct nd_mapping *nd_mapping = &nd_region->mapping[i];
diff --git a/include/linux/memregion.h b/include/linux/memregion.h
index 945646bde825..428635562302 100644
--- a/include/linux/memregion.h
+++ b/include/linux/memregion.h
@@ -27,6 +27,9 @@ static inline void memregion_free(int id)
/**
* cpu_cache_invalidate_memregion - drop any CPU cached data for
* memregion
+ * @start: start physical address of the target memory region.
+ * @len: length of the target memory region. -1 for all the regions of
+ * the target type.
*
* Perform cache maintenance after a memory event / operation that
* changes the contents of physical memory in a cache-incoherent manner.
@@ -45,7 +48,7 @@ static inline void memregion_free(int id)
* the cache maintenance.
*/
#ifdef CONFIG_ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION
-int cpu_cache_invalidate_memregion(void);
+int cpu_cache_invalidate_memregion(phys_addr_t start, size_t len);
bool cpu_cache_has_invalidate_memregion(void);
#else
static inline bool cpu_cache_has_invalidate_memregion(void)
@@ -53,7 +56,7 @@ static inline bool cpu_cache_has_invalidate_memregion(void)
return false;
}
-static inline int cpu_cache_invalidate_memregion(void)
+static inline int cpu_cache_invalidate_memregion(phys_addr_t start, size_t len)
{
WARN_ON_ONCE("CPU cache invalidation required");
return -ENXIO;
--
2.48.1
next prev parent reply other threads:[~2025-08-20 10:30 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-20 10:29 [PATCH v3 0/8] Cache coherency management subsystem Jonathan Cameron
2025-08-20 10:29 ` [PATCH v3 1/8] memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() Jonathan Cameron
2025-09-08 20:45 ` dan.j.williams
2025-08-20 10:29 ` Jonathan Cameron [this message]
2025-09-08 20:51 ` [PATCH v3 2/8] memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() dan.j.williams
2025-08-20 10:29 ` [PATCH v3 3/8] lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-08-20 17:44 ` Randy Dunlap
2025-09-03 16:25 ` Catalin Marinas
2025-09-08 20:59 ` dan.j.williams
2025-10-08 16:45 ` Jonathan Cameron
2025-08-20 10:29 ` [PATCH v3 4/8] MAINTAINERS: Add Jonathan Cameron to drivers/cache Jonathan Cameron
2025-10-01 23:31 ` Conor Dooley
2025-08-20 10:29 ` [PATCH v3 5/8] arm64: Select GENERIC_CPU_CACHE_MAINTENANCE and ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-09-03 16:25 ` Catalin Marinas
2025-08-20 10:29 ` [PATCH v3 6/8] cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent Jonathan Cameron
2025-09-08 22:04 ` dan.j.williams
2025-10-08 14:13 ` Jonathan Cameron
2025-08-20 10:29 ` [PATCH v3 7/8] acpi: PoC of Cache control via ACPI0019 and _DSM Jonathan Cameron
2025-08-20 17:07 ` Randy Dunlap
2025-08-20 10:29 ` [PATCH v3 8/8] Hack: Pretend we have PSCI 1.2 Jonathan Cameron
2025-10-20 6:57 ` [PATCH v3 0/8] Cache coherency management subsystem Yushan Wang
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