From: Yunhui Cui <cuiyunhui@bytedance.com>
To: yury.norov@gmail.com, linux@rasmusvillemoes.dk,
paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
dennis@kernel.org, tj@kernel.org, cl@gentwo.org,
linux-mm@kvack.org
Cc: Yunhui Cui <cuiyunhui@bytedance.com>
Subject: [PATCH 0/2] riscv: introduce percpu.h
Date: Tue, 19 Aug 2025 21:50:05 +0800 [thread overview]
Message-ID: <20250819135007.85646-1-cuiyunhui@bytedance.com> (raw)
Current per-CPU operations rely on generic code using raw_local_irq_save(),
which incurs significant overhead. This patch optimizes 32/64-bit paths with
RISC-V atomic instructions, reducing overhead.
RISC-V lacks lr/sc.b/h support; without ZABHA, emulating 8/16-bit operations
via lr/sc.w would require complex mask logic. However, data shows 8/16-bit
per-CPU operations are extremely rare (single-digit counts in boot and
hackbench tests). Thus, we let 8/16-bit ops fall back to the generic
implementation, avoiding unnecessary complexity. 32/64-bit ops use direct
atomic instructions for performance.
Yunhui Cui (2):
riscv: remove irqflags.h inclusion in asm/bitops.h
riscv: introduce percpu.h into include/asm
arch/riscv/include/asm/bitops.h | 1 -
arch/riscv/include/asm/percpu.h | 138 ++++++++++++++++++++++++++++++++
2 files changed, 138 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/include/asm/percpu.h
--
2.39.5
next reply other threads:[~2025-08-19 13:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-19 13:50 Yunhui Cui [this message]
2025-08-19 13:50 ` [PATCH 1/2] riscv: remove irqflags.h inclusion in asm/bitops.h Yunhui Cui
2025-08-19 13:50 ` [PATCH 2/2] riscv: introduce percpu.h into include/asm Yunhui Cui
2025-08-20 6:44 ` kernel test robot
2025-08-20 17:18 ` kernel test robot
2025-08-20 23:26 ` Christoph Lameter (Ampere)
2025-08-21 8:01 ` [External] " yunhui cui
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