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[108.26.215.125]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7e67f7064b0sm717855685a.54.2025.08.05.12.39.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Aug 2025 12:39:57 -0700 (PDT) From: Jesse Taube To: linux-riscv@lists.infradead.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Oleg Nesterov , Kees Cook , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , "Liang, Kan" , Shuah Khan , Jesse Taube , Himanshu Chauhan , Charlie Jenkins , Samuel Holland , Conor Dooley , Deepak Gupta , Andrew Jones , Atish Patra , Anup Patel , Mayuresh Chitale , Evan Green , WangYuli , Huacai Chen , Arnd Bergmann , Andrew Morton , Luis Chamberlain , "Mike Rapoport (Microsoft)" , Nam Cao , Yunhui Cui , Joel Granados , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Sebastian Andrzej Siewior , Celeste Liu , Chunyan Zhang , Nylon Chen , Thomas Gleixner , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , Vincenzo Frascino , Joey Gouly , Akihiko Odaki , Ravi Bangoria , linux-kernel@vger.kernel.org, linux-mm@kvack.org, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH 0/8] riscv: add initial support for hardware breakpoints Date: Tue, 5 Aug 2025 12:39:47 -0700 Message-ID: <20250805193955.798277-1-jesse@rivosinc.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspam-User: X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: 1A33840007 X-Stat-Signature: ic5rbz745g1dpohhq79az5qd85hr1xk5 X-HE-Tag: 1754422798-1213 X-HE-Meta: U2FsdGVkX19jOwnciJzdpX9cGp1Cqk7GBJdXx8hrbvPhv0Z9Or14XjVH5Ugt1SAVqJvJAFriZXrDnEA7724PRekGqr9dMxHRjAVdaHzNgPeQrgJuqacCKGR/IFGeEwGygEak0S88mlnEkfP4q57gSE6uC+5DpdSNLjFIX6KKshD6yxy271G3nzsDYUI215ZRqcfRCMd4EBj7i3omSzic99MqATaczNGmxj/BKX+4wABQwTnpK6HDiCf3vpA26Wu5O0B14jDs+Jr4kCpdr2pdp54iWAYvy4AnURXKInF5N4RgQdbLZN3aet6/VItE/TBPJjD97ch3+XpB5h5gExlcYknHmVKjVhgwgg1gwzMTgGsb8bRhRa2QU2WjjO2HYC/fgK9lRw5WxTT5/GPnjYcFJv6wI1DI4qJ2sxvNpZ3ofRbWjWuSpVDTw2Ey3BrrHxMqmMVQqD47EpXgYVtqgPO/1aHTY1CwlevPBdNUMehdZLjZ77TNxYv0q/xkFIVnzG4hd/9uGmjuGntmsH9G4gIGV0ieXEZpIrprFuhQyYCy1Ah4z2lyhvxA5+hZkwq3mDC9AtOPkYfCM2KR5sMQ4HJY0SmAckGYkVfJsgc0aFOumoo3k9cUDhodWfjVRVDvpkgOCrVM1tY/4AG0Irxx0N1Vp6mHq+vONmH1viXHB8eMmaKv12X9+6Xv3GfpuyS9+k4oNdN2D2HxLkCJ/Aqqje2bEUb9wW/gMBqarh0+o/hW9ww+ZQ6nM02kNVxTp195SaTfjEE1pk0QT2FHIXmgirH5XSeBdX7XeOIzdQsx8bqXK4oMYF8Aev6G9nShoKmXQGYNShB9hmw6/9GmucuPenLMy60efd34WVEdVo3kWPpDYD1MNJ8YlTbmGG3UMA99fZ77QSz3MJlaNukWG4ZPyznZ+6mvi8FwnVhkwW/2iDlqilVGRTntA9RvwuQWo4N0+5dj8tOQ0waMA728l07Fo2m a+i4LDRC WvJJlBHDZdEr6J+L1CXoPnI2O2s3Yc4+QTVYUcAaBJUVnp5/plPFSL1sJSk0Gh3WxBHnET4NWBfs7pYfqX3xDH/9p3xgM94rFnr8B61kunsTd35+3cFZ9XFf6vf0YAHDLt2SPbh8yxcgLDt01PMD+MwEPiMMmdx3Kt4aCk7ybhcF5Ws8GUssxY4ULatT5+jsRjNPj9NL73WMLkxI33BBxqBwsUtRm1/7bBmBxL57u3HIWLfxt0uheD5BJOF4+LyZOUTtFIjgLUJ1+xtkMocBFtSl4BvJCk+idf5Mr2y3KbB4v93e60PdTQ6KusoI6HMMYTtTTIzRgXt8HXFS9qjpswuHVJF8SQS/i57zTDKYjXnkx1ibjgIsyKOhrQoebEWJRZCtCSlIG+fAY0cdyFGqtrPINXbzUbpa5EuGz X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patchset adds initial support for hardware breakpoints and watchpoints to the RISC-V architecture. The framework is built on top of perf subsystem and SBI debug trigger extension. Currently following features are not supported and are in works: - icount for single stepping - Virtualization of debug triggers - kernel space debug triggers The SBI debug trigger extension can be found at: https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/src/ext-debug-triggers.adoc The Sdtrig ISA is part of RISC-V debug specification which can be found at: https://github.com/riscv/riscv-debug-spec based off the original RFC by Himanshu Chauhan here: https://lore.kernel.org/lkml/20240222125059.13331-1-hchauhan@ventanamicro.com/ Second RFC by Jesse Taube here: https://lore.kernel.org/lkml/20250722173829.984082-1-jesse@rivosinc.com/ Himanshu Chauhan (2): riscv: Add SBI debug trigger extension and function ids riscv: Introduce support for hardware break/watchpoints Jesse Taube (6): riscv: Add insn.c, consolidate instruction decoding riscv: insn: Add get_insn_nofault riscv: hw_breakpoint: Use icount for single stepping riscv: ptrace: Add hw breakpoint support riscv: ptrace: Add hw breakpoint regset selftests: riscv: Add test for hardware breakpoints arch/riscv/Kconfig | 13 + arch/riscv/include/asm/bug.h | 12 - arch/riscv/include/asm/hw_breakpoint.h | 59 ++ arch/riscv/include/asm/insn.h | 132 ++- arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/processor.h | 4 + arch/riscv/include/asm/sbi.h | 33 +- arch/riscv/include/uapi/asm/ptrace.h | 9 + arch/riscv/kernel/Makefile | 2 + arch/riscv/kernel/hw_breakpoint.c | 769 ++++++++++++++++++ arch/riscv/kernel/insn.c | 165 ++++ arch/riscv/kernel/kgdb.c | 102 +-- arch/riscv/kernel/probes/kprobes.c | 1 + arch/riscv/kernel/process.c | 4 + arch/riscv/kernel/ptrace.c | 169 ++++ arch/riscv/kernel/traps.c | 11 +- arch/riscv/kernel/traps_misaligned.c | 93 +-- include/uapi/linux/elf.h | 2 + tools/include/uapi/linux/elf.h | 1 + tools/perf/tests/tests.h | 3 +- tools/testing/selftests/riscv/Makefile | 2 +- .../selftests/riscv/breakpoints/.gitignore | 1 + .../selftests/riscv/breakpoints/Makefile | 12 + .../riscv/breakpoints/breakpoint_test.c | 246 ++++++ 24 files changed, 1657 insertions(+), 191 deletions(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c create mode 100644 arch/riscv/kernel/insn.c create mode 100644 tools/testing/selftests/riscv/breakpoints/.gitignore create mode 100644 tools/testing/selftests/riscv/breakpoints/Makefile create mode 100644 tools/testing/selftests/riscv/breakpoints/breakpoint_test.c -- 2.43.0