From: Peter Zijlstra <peterz@infradead.org>
To: dan.j.williams@intel.com
Cc: "H. Peter Anvin" <hpa@zytor.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
james.morse@arm.com, linux-cxl@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
gregkh@linuxfoundation.org, Will Deacon <will@kernel.org>,
Davidlohr Bueso <dave@stgolabs.net>,
Yicong Yang <yangyicong@huawei.com>,
linuxarm@huawei.com, Yushan Wang <wangyushan12@huawei.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
x86@kernel.org, Andy Lutomirski <luto@kernel.org>
Subject: Re: [PATCH v2 0/8] Cache coherency management subsystem
Date: Thu, 10 Jul 2025 12:56:22 +0200 [thread overview]
Message-ID: <20250710105622.GA542000@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <686f4e20c57cd_1d3d100b7@dwillia2-xfh.jf.intel.com.notmuch>
On Wed, Jul 09, 2025 at 10:22:40PM -0700, dan.j.williams@intel.com wrote:
> "Regular?", no. Something is wrong if you are doing this regularly. In
> current CXL systems the expectation is to suffer a WBINVD event once per
> server provisioning event.
Ok, so how about we strictly track this once, and when it happens more
than this once, we error out hard?
> Now, there is a nascent capability called "Dynamic Capacity Devices"
> (DCD) where the CXL configuration is able to change at runtime with
> multiple hosts sharing a pool of memory. Each time the physical memory
> capacity changes, cache management is needed.
>
> For DCD, I think the negative effects of WBINVD are a *useful* stick to
> move device vendors to stop relying on software to solve this problem.
> They can implement an existing CXL protocol where the device tells CPUs
> and other CXL.cache agents to invalidate the physical address ranges
> that the device owns.
>
> In other words, if WBINVD makes DCD inviable that is a useful outcome
> because it motivates unburdening Linux long term with this problem.
Per the above, I suggest we not support this feature *AT*ALL* until an
alternative to WBINVD is provided.
> In the near term though, current CXL platforms that do not support
> device-initiated-invalidate still need coarse cache management for that
> original infrequent provisioning events. Folks that want to go further
> and attempt frequent DCD events with WBINVD get to keep all the pieces.
I would strongly prefer those pieces to include WARNs and or worse.
next prev parent reply other threads:[~2025-07-10 10:56 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 15:47 Jonathan Cameron
2025-06-24 15:47 ` [PATCH v2 1/8] memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() Jonathan Cameron
2025-07-09 19:46 ` Davidlohr Bueso
2025-07-09 22:31 ` dan.j.williams
2025-07-11 11:54 ` Jonathan Cameron
2025-06-24 15:47 ` [PATCH v2 2/8] generic: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-06-24 16:16 ` Greg KH
2025-06-25 16:46 ` Jonathan Cameron
2025-07-10 5:57 ` dan.j.williams
2025-07-10 6:01 ` H. Peter Anvin
2025-07-11 11:53 ` Jonathan Cameron
2025-07-11 11:52 ` Jonathan Cameron
2025-08-07 16:07 ` Jonathan Cameron
2025-06-24 15:47 ` [PATCH v2 3/8] cache: coherency core registration and instance handling Jonathan Cameron
2025-06-24 15:48 ` [PATCH v2 4/8] MAINTAINERS: Add Jonathan Cameron to drivers/cache Jonathan Cameron
2025-06-24 15:48 ` [PATCH v2 5/8] arm64: Select GENERIC_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-06-25 16:21 ` kernel test robot
2025-06-28 7:10 ` kernel test robot
2025-06-24 15:48 ` [PATCH v2 6/8] cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent Jonathan Cameron
2025-06-24 17:18 ` Randy Dunlap
2025-06-24 15:48 ` [RFC v2 7/8] acpi: PoC of Cache control via ACPI0019 and _DSM Jonathan Cameron
2025-06-24 15:48 ` [PATCH v2 8/8] Hack: Pretend we have PSCI 1.2 Jonathan Cameron
2025-06-25 8:52 ` [PATCH v2 0/8] Cache coherency management subsystem Peter Zijlstra
2025-06-25 9:12 ` H. Peter Anvin
2025-06-25 9:31 ` Peter Zijlstra
2025-06-25 17:03 ` Jonathan Cameron
2025-06-26 9:55 ` Jonathan Cameron
2025-07-10 5:32 ` dan.j.williams
2025-07-10 10:59 ` Peter Zijlstra
2025-07-10 18:36 ` dan.j.williams
2025-07-10 5:22 ` dan.j.williams
2025-07-10 5:31 ` H. Peter Anvin
2025-07-10 10:56 ` Peter Zijlstra [this message]
2025-07-10 18:45 ` dan.j.williams
2025-07-10 18:55 ` H. Peter Anvin
2025-07-10 19:11 ` dan.j.williams
2025-07-10 19:16 ` H. Peter Anvin
2025-07-09 19:53 ` Davidlohr Bueso
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