From: David Laight <david.laight.linux@gmail.com>
To: Vegard Nossum <vegard.nossum@oracle.com>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
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Subject: Re: [PATCHv8 02/17] x86/asm: Introduce inline memcpy and memset
Date: Thu, 3 Jul 2025 17:52:20 +0100 [thread overview]
Message-ID: <20250703175220.1cb05c1b@pumpkin> (raw)
In-Reply-To: <78aab15e-5bc2-47cc-ac1c-5a348bff0e17@oracle.com>
On Thu, 3 Jul 2025 15:33:16 +0200
Vegard Nossum <vegard.nossum@oracle.com> wrote:
> On 03/07/2025 14:15, David Laight wrote:
> > On Thu, 3 Jul 2025 13:39:57 +0300
> > "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> wrote:
> >> On Thu, Jul 03, 2025 at 09:44:17AM +0100, David Laight wrote:
> >>> On Tue, 1 Jul 2025 12:58:31 +0300
> >>> "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> wrote:
> >>>> diff --git a/arch/x86/lib/clear_page_64.S b/arch/x86/lib/clear_page_64.S
> >>>> index a508e4a8c66a..47b613690f84 100644
> >>>> --- a/arch/x86/lib/clear_page_64.S
> >>>> +++ b/arch/x86/lib/clear_page_64.S
> >>>> @@ -55,17 +55,26 @@ SYM_FUNC_END(clear_page_erms)
> >>>> EXPORT_SYMBOL_GPL(clear_page_erms)
> >>>>
> >>>> /*
> >>>> - * Default clear user-space.
> >>>> + * Default memset.
> >>>> * Input:
> >>>> * rdi destination
> >>>> + * rsi scratch
> >>>> * rcx count
> >>>> - * rax is zero
> >>>> + * al is value
> >>>> *
> >>>> * Output:
> >>>> * rcx: uncleared bytes or 0 if successful.
> >>>> + * rdx: clobbered
> >>>> */
> >>>> SYM_FUNC_START(rep_stos_alternative)
> >>>> ANNOTATE_NOENDBR
> >>>> +
> >>>> + movzbq %al, %rsi
> >>>> + movabs $0x0101010101010101, %rax
> >>>> +
> >>>> + /* RDX:RAX = RAX * RSI */
> >>>> + mulq %rsi
> >>>
> >>> NAK - you can't do that here.
> >>> Neither %rsi nor %rdx can be trashed.
> >>> The function has a very explicit calling convention.
>
> That's why we have the clobbers... see below
>
> >> What calling convention? We change the only caller to confirm to this.
> >
> > The one that is implicit in:
> >
> >>>> + asm volatile("1:\n\t"
> >>>> + ALT_64("rep stosb",
> >>>> + "call rep_stos_alternative", ALT_NOT(X86_FEATURE_FSRM))
> >>>> + "2:\n\t"
> >>>> + _ASM_EXTABLE_UA(1b, 2b)
> >>>> + : "+c" (len), "+D" (addr), ASM_CALL_CONSTRAINT
> >>>> + : "a" ((uint8_t)v)
> >
> > The called function is only allowed to change the registers that
> > 'rep stosb' uses - except it can access (but not change)
> > all of %rax - not just %al.
> >
> > See: https://godbolt.org/z/3fnrT3x9r
> > In particular note that 'do_mset' must not change %rax.
> >
> > This is very specific and is done so that the compiler can use
> > all the registers.
>
> I feel like you trimmed off the clobbers from the asm() in the context
> above. For reference, it is:
>
> + : "memory", _ASM_SI, _ASM_DX);
I'm sure they weren't there...
Enough clobbers will 'un-break' it - but that isn't the point.
Linux will reject the patch if he reads it.
The whole point about the function is that it is as direct a replacement
for 'rep stos/movsb' as possible.
>
> I'm not saying this can't be optimized, but that doesn't seem to be your
> complaint -- you say "the called function is only allowed to change
> ...", but this is not true when we have the clobbers, right?
You can't change %rax either - not without a clobber.
Oh, and even with your version you only clobbers for %rax and %rdx.
There is no need to use both %rsi and %rdx.
The performance is a different problem.
And the extra clobbers are likely to matter.
x86 really doesn't have many registers.
David
>
> This is exactly what I fixed with my v7 fixlet to this patch:
>
> https://lore.kernel.org/all/1b96b0ca-5c14-4271-86c1-c305bf052b16@oracle.com/
>
>
> Vegard
next prev parent reply other threads:[~2025-07-03 16:52 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250701095849.2360685-1-kirill.shutemov@linux.intel.com>
[not found] ` <20250701095849.2360685-4-kirill.shutemov@linux.intel.com>
2025-07-01 18:44 ` [PATCHv8 03/17] x86/alternatives: Disable LASS when patching kernel alternatives Sohil Mehta
[not found] ` <20250701095849.2360685-12-kirill.shutemov@linux.intel.com>
2025-07-01 22:51 ` [PATCHv8 11/17] x86/cpu: Set LASS CR4 bit as pinning sensitive Sohil Mehta
[not found] ` <20250701095849.2360685-16-kirill.shutemov@linux.intel.com>
2025-07-01 23:03 ` [PATCHv8 15/17] x86/cpu: Make LAM depend on LASS Sohil Mehta
[not found] ` <20250701095849.2360685-5-kirill.shutemov@linux.intel.com>
2025-07-01 19:03 ` [PATCHv8 04/17] x86/cpu: Defer CR pinning setup until after EFI initialization Sohil Mehta
2025-07-02 9:47 ` Kirill A. Shutemov
2025-07-01 23:10 ` Dave Hansen
2025-07-02 10:05 ` Kirill A. Shutemov
2025-07-04 12:23 ` Kirill A. Shutemov
[not found] ` <20250701095849.2360685-18-kirill.shutemov@linux.intel.com>
2025-07-01 23:13 ` [PATCHv8 17/17] x86: Re-enable Linear Address Masking Sohil Mehta
[not found] ` <20250701095849.2360685-13-kirill.shutemov@linux.intel.com>
2025-07-02 0:36 ` [PATCHv8 12/17] x86/traps: Communicate a LASS violation in #GP message Sohil Mehta
2025-07-02 10:10 ` Kirill A. Shutemov
[not found] ` <20250701095849.2360685-14-kirill.shutemov@linux.intel.com>
2025-07-02 0:54 ` [PATCHv8 13/17] x86/traps: Generalize #GP address decode and hint code Sohil Mehta
[not found] ` <20250701095849.2360685-15-kirill.shutemov@linux.intel.com>
2025-07-02 1:35 ` [PATCHv8 14/17] x86/traps: Handle LASS thrown #SS Sohil Mehta
2025-07-02 2:00 ` H. Peter Anvin
2025-07-02 2:06 ` H. Peter Anvin
2025-07-02 10:17 ` Kirill A. Shutemov
2025-07-02 14:37 ` H. Peter Anvin
2025-07-02 14:47 ` Kirill A. Shutemov
2025-07-02 17:10 ` H. Peter Anvin
2025-07-02 23:42 ` Andrew Cooper
2025-07-03 0:44 ` H. Peter Anvin
2025-07-06 9:22 ` David Laight
2025-07-06 15:07 ` H. Peter Anvin
2025-07-02 13:27 ` Kirill A. Shutemov
2025-07-02 17:56 ` Sohil Mehta
2025-07-03 10:40 ` Kirill A. Shutemov
2025-07-02 20:05 ` Sohil Mehta
2025-07-03 11:31 ` Kirill A. Shutemov
2025-07-03 20:12 ` Sohil Mehta
2025-07-04 9:23 ` Kirill A. Shutemov
[not found] ` <20250701095849.2360685-3-kirill.shutemov@linux.intel.com>
2025-07-03 8:44 ` [PATCHv8 02/17] x86/asm: Introduce inline memcpy and memset David Laight
2025-07-03 10:39 ` Kirill A. Shutemov
2025-07-03 12:15 ` David Laight
2025-07-03 13:33 ` Vegard Nossum
2025-07-03 16:52 ` David Laight [this message]
2025-07-03 14:10 ` Kirill A. Shutemov
2025-07-03 17:02 ` David Laight
2025-07-03 17:13 ` Dave Hansen
2025-07-04 9:04 ` Kirill A. Shutemov
2025-07-06 9:13 ` David Laight
2025-07-07 8:02 ` Kirill A. Shutemov
2025-07-07 9:33 ` David Laight
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