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Tue, 17 Jun 2025 20:45:21 -0700 (PDT) From: Yunhui Cui To: yury.norov@gmail.com, linux@rasmusvillemoes.dk, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, linux-mm@kvack.org Cc: Yunhui Cui Subject: [PATCH RFC 2/2] riscv: introduce percpu.h into include/asm Date: Wed, 18 Jun 2025 11:43:28 +0800 Message-Id: <20250618034328.21904-2-cuiyunhui@bytedance.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20250618034328.21904-1-cuiyunhui@bytedance.com> References: <20250618034328.21904-1-cuiyunhui@bytedance.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam05 X-Rspamd-Queue-Id: AA435C0006 X-Stat-Signature: qez8fiofdcydspsn5bjqfwfkdboc3im1 X-Rspam-User: X-HE-Tag: 1750218323-476535 X-HE-Meta: U2FsdGVkX1+61AkJx9DMnkrd82eMdjYO646u8aa+aNUsVfhYJZuGt9i1ah2V0QLaETHWyqq2hPXwwy+3v245bUILVWCTTWklV50W27QCtQpsmrTGUqU6tzkCtYzTDVDxyGAE3sBQ10CxSOc7pcZxiD1d8SUT3sGOvIzwgs6QkW9sYAN3mL4UB+eHfz1D1z3tclzab1vUm50ZktV0D3FIRENxGJXhgM/HeZ8DE7vz6ZE15P7FB+Gbd/I9lXjEc53A3hygxqMMmubRHOwOP7yVibkABPYELyYOmjYFwwAy+ahkEp+6lRyO/BMlcbZK0EEU58T3v7W9TgJA/ObQQ8kiLiGKZu+txyEXKFMl3/ZeNvl6TyXz+euxFRXXZfchp6zEumrc7FcDxqOl6NyFOqei60fwCEeTVvUFYvdnHciMwLl4jAadu/ygdtbwu4VYpqSxWCgCTv8nMTbtq+KGEZVui5IEOb++k+m26a/EIoMyIvXMknPkPfEv5rXeb8aQ1r2eDAiw5dYB6l9YNbSvVSZJBT8CoZhplsEmmR0jmV0sBV/eXJZbpaHaSjD+V65ZW13+mpD275as3IhIMP4BegXeuuJUrvxqTkcTZjYfS4BTL+KU/nceRNV2nBLvEkoH87Ggsv9G6zSJ8Y0R84JHOLqELia0Pp1nrG7ijOvgDvEXrTUJrdePCpdie/bPtdh0YUxW2zYR0csl8Se0wvcbQfIJlF2ocUeKkcOZEDyMmjWTgeP0dbj9fv2sc0ISt/z1nzR8nlKv2VWR/XRw4tfijsPAZu6kRjVV8LQHMPvwPZYAwWFcaQLxSTorII9KJe2lHUN/sGmNKVmXdVDzUgu5rABFKhKvc6SvpmgTOvg3c76F54Ch9jLD4q/IycKBg6qMPgco4w9hNEdUyAJQXPQSeM3RibHdBQRblT3e9hN2nYCahMyKlU1TH9joH3rzXwCSeZcLdx0zbGNuWCUzMTfowcY ba9tuqI9 lIMuZouarPJYLJbZpdOnSuNLV+0fmhq5phfuddrkKyYuYVpnzueyphoBnO8XqGHxGhDMTgv3fTzkfPG1OxxrsIhbV76EhVDWZDRMSIP6+ypFn+rlbl260ehbMfHM0HSBreJ0wUz8jtQaXnK+RMYBNb5WyGEeLJW+Gl4SKVHfBYCCln4vNzfsVelhclQ7TkP2LVqZR1hTDWttFbI+B4D850CyxNQofaVKdVc5EkRc1gAwPo1WwV8uJJKblAZ44fudJ9Vrwy7KUteqrkDgaD00rbDM7746uWG7Jimdk+9UOLZ72IiwewD/8V/54TEL+7xBr13LM1p8jaHUYvXxvW/lSU6d2qWhO1IsaGlzLSbA/LxS4PKz8tZ5z3GLpxhj0kGl3Zt6I X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Current percpu operations rely on generic implementations, where raw_local_irq_save() introduces substantial overhead. Optimization is achieved through atomic operations and preemption disabling. Signed-off-by: Yunhui Cui --- arch/riscv/include/asm/percpu.h | 138 ++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 arch/riscv/include/asm/percpu.h diff --git a/arch/riscv/include/asm/percpu.h b/arch/riscv/include/asm/percpu.h new file mode 100644 index 0000000000000..423c0d01f874c --- /dev/null +++ b/arch/riscv/include/asm/percpu.h @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __ASM_PERCPU_H +#define __ASM_PERCPU_H + +#include + +#define PERCPU_RW_OPS(sz) \ +static inline unsigned long __percpu_read_##sz(void *ptr) \ +{ \ + return READ_ONCE(*(u##sz *)ptr); \ +} \ + \ +static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ +{ \ + WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ +} + +#define __PERCPU_AMO_OP_CASE(sfx, name, sz, amo_insn) \ +static inline void \ +__percpu_##name##_amo_case_##sz(void *ptr, unsigned long val) \ +{ \ + asm volatile ( \ + "amo" #amo_insn #sfx " zero, %[val], %[ptr]" \ + : [ptr] "+A" (*(u##sz *)ptr) \ + : [val] "r" ((u##sz)(val)) \ + : "memory"); \ +} + +#define __PERCPU_AMO_RET_OP_CASE(sfx, name, sz, amo_insn) \ +static inline u##sz \ +__percpu_##name##_return_amo_case_##sz(void *ptr, unsigned long val) \ +{ \ + register u##sz ret; \ + \ + asm volatile ( \ + "amo" #amo_insn #sfx " %[ret], %[val], %[ptr]" \ + : [ptr] "+A" (*(u##sz *)ptr), [ret] "=r" (ret) \ + : [val] "r" ((u##sz)(val)) \ + : "memory"); \ + \ + return ret + val; \ +} + +#define PERCPU_OP(name, amo_insn) \ + __PERCPU_AMO_OP_CASE(.b, name, 8, amo_insn) \ + __PERCPU_AMO_OP_CASE(.h, name, 16, amo_insn) \ + __PERCPU_AMO_OP_CASE(.w, name, 32, amo_insn) \ + __PERCPU_AMO_OP_CASE(.d, name, 64, amo_insn) \ + +#define PERCPU_RET_OP(name, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.b, name, 8, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.h, name, 16, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.w, name, 32, amo_insn) \ + __PERCPU_AMO_RET_OP_CASE(.d, name, 64, amo_insn) + +PERCPU_RW_OPS(8) +PERCPU_RW_OPS(16) +PERCPU_RW_OPS(32) +PERCPU_RW_OPS(64) + +PERCPU_OP(add, add) +PERCPU_OP(andnot, and) +PERCPU_OP(or, or) +PERCPU_RET_OP(add, add) + +#undef PERCPU_RW_OPS +#undef __PERCPU_AMO_OP_CASE +#undef __PERCPU_AMO_RET_OP_CASE +#undef PERCPU_OP +#undef PERCPU_RET_OP + +#define _pcp_protect(op, pcp, ...) \ +({ \ + preempt_disable_notrace(); \ + op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \ + preempt_enable_notrace(); \ +}) + +#define _pcp_protect_return(op, pcp, args...) \ +({ \ + typeof(pcp) __retval; \ + preempt_disable_notrace(); \ + __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \ + preempt_enable_notrace(); \ + __retval; \ +}) + +#define this_cpu_read_1(pcp) _pcp_protect_return(__percpu_read_8, pcp) +#define this_cpu_read_2(pcp) _pcp_protect_return(__percpu_read_16, pcp) +#define this_cpu_read_4(pcp) _pcp_protect_return(__percpu_read_32, pcp) +#define this_cpu_read_8(pcp) _pcp_protect_return(__percpu_read_64, pcp) + +#define this_cpu_write_1(pcp, val) _pcp_protect(__percpu_write_8, pcp, (unsigned long)val) +#define this_cpu_write_2(pcp, val) _pcp_protect(__percpu_write_16, pcp, (unsigned long)val) +#define this_cpu_write_4(pcp, val) _pcp_protect(__percpu_write_32, pcp, (unsigned long)val) +#define this_cpu_write_8(pcp, val) _pcp_protect(__percpu_write_64, pcp, (unsigned long)val) + +#define this_cpu_add_1(pcp, val) _pcp_protect(__percpu_add_amo_case_8, pcp, val) +#define this_cpu_add_2(pcp, val) _pcp_protect(__percpu_add_amo_case_16, pcp, val) +#define this_cpu_add_4(pcp, val) _pcp_protect(__percpu_add_amo_case_32, pcp, val) +#define this_cpu_add_8(pcp, val) _pcp_protect(__percpu_add_amo_case_64, pcp, val) + +#define this_cpu_add_return_1(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_8, pcp, val) + +#define this_cpu_add_return_2(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_16, pcp, val) + +#define this_cpu_add_return_4(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_32, pcp, val) + +#define this_cpu_add_return_8(pcp, val) \ +_pcp_protect_return(__percpu_add_return_amo_case_64, pcp, val) + +#define this_cpu_and_1(pcp, val) _pcp_protect(__percpu_andnot_amo_case_8, pcp, ~val) +#define this_cpu_and_2(pcp, val) _pcp_protect(__percpu_andnot_amo_case_16, pcp, ~val) +#define this_cpu_and_4(pcp, val) _pcp_protect(__percpu_andnot_amo_case_32, pcp, ~val) +#define this_cpu_and_8(pcp, val) _pcp_protect(__percpu_andnot_amo_case_64, pcp, ~val) + +#define this_cpu_or_1(pcp, val) _pcp_protect(__percpu_or_amo_case_8, pcp, val) +#define this_cpu_or_2(pcp, val) _pcp_protect(__percpu_or_amo_case_16, pcp, val) +#define this_cpu_or_4(pcp, val) _pcp_protect(__percpu_or_amo_case_32, pcp, val) +#define this_cpu_or_8(pcp, val) _pcp_protect(__percpu_or_amo_case_64, pcp, val) + +#define this_cpu_xchg_1(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val) +#define this_cpu_xchg_2(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val) +#define this_cpu_xchg_4(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val) +#define this_cpu_xchg_8(pcp, val) _pcp_protect_return(xchg_relaxed, pcp, val) + +#define this_cpu_cmpxchg_1(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) +#define this_cpu_cmpxchg_2(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) +#define this_cpu_cmpxchg_4(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) +#define this_cpu_cmpxchg_8(pcp, o, n) _pcp_protect_return(cmpxchg_relaxed, pcp, o, n) + +#include + +#endif /* __ASM_PERCPU_H */ -- 2.39.5