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d=hostedemail.com; s=arc-20220608; t=1747703058; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:references; bh=8S/5EH27m6j05Cmgx6ExHJXEA5ux7uArhMIuoRsJSwM=; b=bKxhubvBvAjR0XFRIuT9s5Oh5O8sVuGrRQkh2meMiWc3lc8Cs+AtRgQXGcKRc76U3WB+6O CN2AizbtTGvwdXXLZe/2akTVyDgfg/3SL3GxaL4pJ83BCqGpanMRH/wzvKgoveAhixDXzI D1v/DmxJJLHbCLAh8L0EAANHnIPW4Fs= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1uHBOc-000000000aB-3VuI; Mon, 19 May 2025 21:03:54 -0400 From: Rik van Riel To: linux-kernel@vger.kernel.org Cc: linux-mm@kvack.org, x86@kernel.org, kernel-team@meta.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, nadav.amit@gmail.com Subject: [RFC v2 PATCH 0/9] Intel RAR TLB invalidation Date: Mon, 19 May 2025 21:02:25 -0400 Message-ID: <20250520010350.1740223-1-riel@surriel.com> X-Mailer: git-send-email 2.49.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspam-User: X-Rspamd-Server: rspam01 X-Rspamd-Queue-Id: AFA781C000D X-Stat-Signature: xbox1bqfkry9mo7kjxabybf569g8tazf X-HE-Tag: 1747703058-231969 X-HE-Meta: U2FsdGVkX1/ONkqLsjMK9U4YYXzzuQ+bwGL4Hd86oc90z4nVAwDDawVEtpXNdjjaHPHRfJcheTSXLxD0XguSmenwPQu4dxbAQjj3Kkfry3kY5eX9C55wnEiEELiAC0tVGKh5ajnDPvzUxpH5KLPaqT/dJCscRtw7PEPrCGQepQrBteKjny72y9fooOlgpDbLrqbClrKvbL251vWpvkp5D9Jl8TCGzowv5bPGZFL6hX+NighEmJ1x7ZlFcLIkeDe0eHyvhWXNkYPEeHK3siIH1yAJIWG9zD/qNgtpKQd01fuNgaiUm9KdqjG8DVxwsyQG2oPHj90pGG1dxrY1onYG4VJkoGEEDUSzU4C9sbilDG4cTOVdkveMQf3/Yun/HMhknU8wOGcaQD2IclqhmYYkxX2HDHpRARCCwjpxlDwqSOJe70J1ZJF1gGwb2Sr9+FPFmvbI8H72aN2fkB33FGhu12pzQztONdpXLNKmxi+mBN/rVQQ12aFJKieKfuWuXgMn/2D6CymX9PGg1edUoYUJF6zuVwKOZ/slb/3zjbAbc7oiYWhAMtcjUwmckuITSWfZ4vVU7e8C2/QBnmoDNQviGaR93pKtchBpaMU8h2jy+uOcECowozmI99Wn5iMkkbyIAna9sXVxP2tuvMBnm6qq18JogS3jgSfLvSios/v+blfIhkDxoyMDg7hKOGVj2ZBrisXqpFamyJrA87SemYl19wv+Gx/6CJ78IL2u9BRy1VnmhZLVPspq475ebPbbqcTy6dr8FYn1Onekagho+TbI7wjOgtNzz18WBAglljevx2F58QvV21zhvdtjJX8Z3hKMCvVEqocMXIXZLwMP3pSdb4gtY63l13FtjjTyLZfA9cZqi5RYxGCAM3pJyxXKzhZVevqJ2NEEVpI83veWHG9NT1tvhOPGN8xxHOmcQqcZfU+lQkKY81+4AKi5fhniEI3hJNunDF7M7AND5g8CQFX c4vE6Ad8 /1s2jaXXdPX8Nc0f9N+0T4WMf6aHROgCcNnrycE8GT2uJP1H/8Yeu0KBjWszmu4jhFATD+E1TTTOfIvfHJts/73FOacuEygCBlN3UsRafy+cAbKnYfYQkIhLtsSyqi/uQVl8LxDJmsB8i0ZSeUc4Q8lu5A+AYsnIfM9qBPWcOZsTihx1FY1MYiMD9rXYRcaWxRY9h2zdqWLikOB07Ex/FPRsSZV5A6if00NB5SemT25+nWE9zC6D+b5IJLoxAdJTjJMqhjP/Ll44cJmRGm+4hN8GJ2Wd6oRZhOiNbXhGny9CGrNOXs9RTGXmCnt/L4Qn7CnfiKLhR+feHyILJwgXLMkq61RyrvOMUp92/ X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: This patch series adds support for IPI-less TLB invalidation using Intel RAR technology. Intel RAR differs from AMD INVLPGB in a few ways: - RAR goes through (emulated?) APIC writes, not instructions - RAR flushes go through a memory table with 64 entries - RAR flushes can be targeted to a cpumask - The RAR functionality must be set up at boot time before it can be used The cpumask targeting has resulted in Intel RAR and AMD INVLPGB having slightly different rules: - Processes with dynamic ASIDs use IPI based shootdowns - INVLPGB: processes with a global ASID - always have the TLB up to date, on every CPU - never need to flush the TLB at context switch time - RAR: processes with global ASIDs - have the TLB up to date on CPUs in the mm_cpumask - can skip a TLB flush at context switch time if the CPU is in the mm_cpumask - need to flush the TLB when scheduled on a cpu not in the mm_cpumask, in case it used to run there before and the TLB has stale entries RAR functionality is present on Sapphire Rapids and newer CPUs. Information about Intel RAR can be found in this whitepaper. https://www.intel.com/content/dam/develop/external/us/en/documents/341431-remote-action-request-white-paper.pdf This patch series is based off a 2019 patch series created by Intel, with patches later in the series modified to fit into the TLB flush code structure we have after AMD INVLPGB functionality was integrated. RFC v2: - Cleanups suggested by Ingo and Nadav (thank you) - Basic RAR code seems to actually work now - Kernel TLB flushes with RAR seem to work correctly - User TLB flushes with RAR are still broken, with two symptoms: - The !is_lazy WARN_ON in leave_mm() is tripped - Random segfaults