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The KVM code is thus restrictive and allows only for the memory that is added to the kernel to be marked as cacheable. The device memory such as on the Grace Hopper/Blackwell systems is interchangeable with DDR memory and retains properties such as cacheability, unaligned accesses, atomics and handling of executable faults. This requires the device memory to be mapped as NORMAL in stage-2. Given that the GPU device memory is not added to the kernel (but is rather VMA mapped through remap_pfn_range() in nvgrace-gpu module which sets VM_PFNMAP), pfn_is_map_memory() is false and thus KVM prevents such memory to be mapped Normal cacheable. The patch aims to solve this use case. A cachebility check is made if the VM_PFNMAP is set in VMA flags by consulting the VMA pgprot value. If the pgprot mapping type is MT_NORMAL, it is safe to be mapped cacheable as the KVM S2 will have the same Normal memory type as the VMA has in the S1 and KVM has no additional responsibility for safety. Checking pgprot as NORMAL is thus a KVM sanity check. Introduce a new variable cacheable_devmem to indicate a safely cacheable mapping. Do not set the device variable when cacheable_devmem is true. This essentially have the effect of setting stage-2 mapping as NORMAL through kvm_pgtable_stage2_map. Add check for COW VM_PFNMAP and refuse such mapping. No additional checks for MTE are needed as kvm_arch_prepare_memory_region() already tests it at an early stage during memslot creation. There would not even be a fault if the memslot is not created. Note when FWB is not enabled, the kernel expects to trivially do cache management by flushing the memory by linearly converting a kvm_pte to phys_addr to a KVA, see kvm_flush_dcache_to_poc(). The cache management thus relies on memory being mapped. So do not allow !FWB. Lastly ARM64_HAS_CACHE_DIC CPU cap allows KVM to avoid flushing the icache and turns icache_inval_pou() into a NOP. This is also thus a requirement of the cacheable PFNMAP feature. Disallow cacheable PFNMAP on hardware with no ARM64_HAS_CACHE_DIC. CC: Oliver Upton Suggested-by: Jason Gunthorpe Suggested-by: Catalin Marinas Suggested-by: David Hildenbrand Signed-off-by: Ankit Agrawal --- arch/arm64/kvm/mmu.c | 43 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index eaac4db61828..3ee2691466fa 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1484,6 +1484,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, bool write_fault, writable, force_pte = false; bool exec_fault, mte_allowed; bool device = false, vfio_allow_any_uc = false; + bool cacheable_devmem = false; unsigned long mmu_seq; phys_addr_t ipa = fault_ipa; struct kvm *kvm = vcpu->kvm; @@ -1621,9 +1622,19 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, vfio_allow_any_uc = vma->vm_flags & VM_ALLOW_ANY_UNCACHED; - if ((vma->vm_flags & VM_PFNMAP) && - mapping_type(vma->vm_page_prot) == MT_NORMAL) - return -EINVAL; + if (vma->vm_flags & VM_PFNMAP) { + /* Reject COW VM_PFNMAP */ + if (is_cow_mapping(vma->vm_flags)) + return -EINVAL; + + /* + * If the VM_PFNMAP is set in VMA flags, do a KVM sanity + * check to see if pgprot mapping type is MT_NORMAL and a + * safely cacheable device memory. + */ + if (mapping_type(vma->vm_page_prot) == MT_NORMAL) + cacheable_devmem = true; + } /* Don't use the VMA after the unlock -- it may have vanished */ vma = NULL; @@ -1656,10 +1667,13 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, * via __kvm_faultin_pfn(), vma_pagesize is set to PAGE_SIZE * and must not be upgraded. * - * In both cases, we don't let transparent_hugepage_adjust() + * Do not set device as the device memory is cacheable. Note + * that such mapping is safe as the KVM S2 will have the same + * Normal memory type as the VMA has in the S1. * change things at the last minute. */ - device = true; + if (!cacheable_devmem) + device = true; } else if (logging_active && !write_fault) { /* * Only actually map the page as writable if this was a write @@ -1741,6 +1755,20 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa, prot |= KVM_PGTABLE_PROT_X; } + /* + * When FWB is unsupported KVM needs to do cache flushes + * (via dcache_clean_inval_poc()) of the underlying memory. This is + * only possible if the memory is already mapped into the kernel map. + * + * Outright reject as the cacheable device memory is not present in + * the kernel map and not suitable for cache management. + */ + if (cacheable_devmem && (!cpus_have_final_cap(ARM64_HAS_CACHE_DIC) || + !stage2_has_fwb(pgt))) { + ret = -EINVAL; + goto out_unlock; + } + /* * Under the premise of getting a FSC_PERM fault, we just need to relax * permissions only if vma_pagesize equals fault_granule. Otherwise, @@ -2222,7 +2250,10 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, } /* Cacheable PFNMAP is not allowed */ - if (mapping_type(vma->vm_page_prot) == MT_NORMAL) { + if (mapping_type(vma->vm_page_prot) == MT_NORMAL && + (!(new->flags & KVM_MEM_ENABLE_CACHEABLE_PFNMAP) || + !stage2_has_fwb(kvm->arch.mmu.pgt) || + !cpus_have_final_cap(ARM64_HAS_CACHE_DIC))) { ret = -EINVAL; break; } -- 2.34.1