From: Will Deacon <will@kernel.org>
To: Ryan Roberts <ryan.roberts@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Pasha Tatashin <pasha.tatashin@soleen.com>,
Andrew Morton <akpm@linux-foundation.org>,
Uladzislau Rezki <urezki@gmail.com>,
Christoph Hellwig <hch@infradead.org>,
David Hildenbrand <david@redhat.com>,
"Matthew Wilcox (Oracle)" <willy@infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Alexandre Ghiti <alexghiti@rivosinc.com>,
Kevin Brodsky <kevin.brodsky@arm.com>,
linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org,
syzbot+5c0d9392e042f41d45c5@syzkaller.appspotmail.com
Subject: Re: [PATCH] arm64/mm: Disable barrier batching in interrupt contexts
Date: Tue, 13 May 2025 21:46:04 +0100 [thread overview]
Message-ID: <20250513204603.GA9866@willie-the-truck> (raw)
In-Reply-To: <20250512102242.4156463-1-ryan.roberts@arm.com>
On Mon, May 12, 2025 at 11:22:40AM +0100, Ryan Roberts wrote:
> Commit 5fdd05efa1cd ("arm64/mm: Batch barriers when updating kernel
> mappings") enabled arm64 kernels to track "lazy mmu mode" using TIF
> flags in order to defer barriers until exiting the mode. At the same
> time, it added warnings to check that pte manipulations were never
> performed in interrupt context, because the tracking implementation
> could not deal with nesting.
>
> But it turns out that some debug features (e.g. KFENCE, DEBUG_PAGEALLOC)
> do manipulate ptes in softirq context, which triggered the warnings.
Hmm. Do we also have to worry about the case where a softirq is triggered
off the back of a hardirq *and* that hardirq is taken while we're in the
middle of e.g. queue_pte_barriers()? In that case, I think we can end
up in strange situations, such as having LAZY_MMU_PENDING set when
LAZY_MMU is clear, although it looks like things still work even in that
case.
Will
next prev parent reply other threads:[~2025-05-13 20:46 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 10:22 Ryan Roberts
2025-05-12 11:00 ` Catalin Marinas
2025-05-12 11:03 ` Ryan Roberts
2025-05-12 11:07 ` David Hildenbrand
2025-05-12 12:00 ` Ryan Roberts
2025-05-12 12:05 ` David Hildenbrand
2025-05-12 12:33 ` Ryan Roberts
2025-05-12 13:14 ` Catalin Marinas
2025-05-12 13:53 ` Ryan Roberts
2025-05-12 14:14 ` Ryan Roberts
2025-05-13 20:46 ` Will Deacon [this message]
2025-05-14 9:29 ` Ryan Roberts
2025-05-14 15:13 ` Will Deacon
2025-05-14 15:14 ` Will Deacon
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