From: Deepak Gupta <debug@rivosinc.com>
To: "Thomas Gleixner" <tglx@linutronix.de>,
"Ingo Molnar" <mingo@redhat.com>,
"Borislav Petkov" <bp@alien8.de>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
"Andrew Morton" <akpm@linux-foundation.org>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
"Vlastimil Babka" <vbabka@suse.cz>,
"Lorenzo Stoakes" <lorenzo.stoakes@oracle.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Conor Dooley" <conor@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Christian Brauner" <brauner@kernel.org>,
"Peter Zijlstra" <peterz@infradead.org>,
"Oleg Nesterov" <oleg@redhat.com>,
"Eric Biederman" <ebiederm@xmission.com>,
"Kees Cook" <kees@kernel.org>, "Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <shuah@kernel.org>, "Jann Horn" <jannh@google.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <benno.lossin@proton.me>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>
Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
alistair.francis@wdc.com, richard.henderson@linaro.org,
jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com,
charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com,
cleger@rivosinc.com, alexghiti@rivosinc.com,
samitolvanen@google.com, broonie@kernel.org,
rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org,
Zong Li <zong.li@sifive.com>, Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v15 24/27] riscv: create a config for shadow stack and landing pad instr support
Date: Fri, 02 May 2025 16:30:55 -0700 [thread overview]
Message-ID: <20250502-v5_user_cfi_series-v15-24-914966471885@rivosinc.com> (raw)
In-Reply-To: <20250502-v5_user_cfi_series-v15-0-914966471885@rivosinc.com>
This patch creates a config for shadow stack support and landing pad instr
support. Shadow stack support and landing instr support can be enabled by
selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires
up path to enumerate CPU support and if cpu support exists, kernel will
support cpu assisted user mode cfi.
If CONFIG_RISCV_USER_CFI is selected, select `ARCH_USES_HIGH_VMA_FLAGS`,
`ARCH_HAS_USER_SHADOW_STACK` and DYNAMIC_SIGFRAME for riscv.
Reviewed-by: Zong Li <zong.li@sifive.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
arch/riscv/Kconfig | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index bbec87b79309..19d5a3d5e0d6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -256,6 +256,27 @@ config ARCH_HAS_BROKEN_DWARF5
# https://github.com/llvm/llvm-project/commit/7ffabb61a5569444b5ac9322e22e5471cc5e4a77
depends on LD_IS_LLD && LLD_VERSION < 180000
+config RISCV_USER_CFI
+ def_bool y
+ bool "riscv userspace control flow integrity"
+ depends on 64BIT && $(cc-option,-mabi=lp64 -march=rv64ima_zicfiss)
+ depends on RISCV_ALTERNATIVE
+ select RISCV_SBI
+ select ARCH_HAS_USER_SHADOW_STACK
+ select ARCH_USES_HIGH_VMA_FLAGS
+ select DYNAMIC_SIGFRAME
+ help
+ Provides CPU assisted control flow integrity to userspace tasks.
+ Control flow integrity is provided by implementing shadow stack for
+ backward edge and indirect branch tracking for forward edge in program.
+ Shadow stack protection is a hardware feature that detects function
+ return address corruption. This helps mitigate ROP attacks.
+ Indirect branch tracking enforces that all indirect branches must land
+ on a landing pad instruction else CPU will fault. This mitigates against
+ JOP / COP attacks. Applications must be enabled to use it, and old user-
+ space does not get protection "for free".
+ default y
+
config ARCH_MMAP_RND_BITS_MIN
default 18 if 64BIT
default 8
--
2.43.0
next prev parent reply other threads:[~2025-05-02 23:32 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-02 23:30 [PATCH v15 00/27] riscv control-flow integrity for usermode Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 01/27] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-05-20 9:15 ` David Hildenbrand
2025-05-02 23:30 ` [PATCH v15 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 03/27] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-05-06 10:10 ` Radim Krčmář
2025-05-15 7:28 ` Alexandre Ghiti
2025-05-15 8:48 ` Radim Krčmář
2025-05-16 15:34 ` Deepak Gupta
2025-05-19 12:39 ` Radim Krčmář
2025-05-02 23:30 ` [PATCH v15 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 07/27] riscv mm: manufacture shadow stack pte Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 08/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 09/27] riscv mmu: write protect and shadow stack Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 10/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 11/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 12/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 13/27] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 14/27] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 15/27] riscv/traps: Introduce software check exception Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 16/27] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 17/27] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 18/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 19/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 20/27] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 21/27] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 22/27] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-05-15 7:10 ` Alexandre Ghiti
2025-05-16 15:16 ` Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 23/27] arch/riscv: compile vdso with landing pad Deepak Gupta
2025-05-02 23:30 ` Deepak Gupta [this message]
2025-05-02 23:30 ` [PATCH v15 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-05-02 23:30 ` [PATCH v15 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
2025-05-20 6:02 ` Charlie Jenkins
2025-05-20 23:49 ` Deepak Gupta
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