From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A6BBC369DC for ; Wed, 30 Apr 2025 00:25:03 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 8018F6B00AA; Tue, 29 Apr 2025 20:25:01 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 7AE2D6B00AB; Tue, 29 Apr 2025 20:25:01 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 604316B00AC; Tue, 29 Apr 2025 20:25:01 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 3A0106B00AA for ; Tue, 29 Apr 2025 20:25:01 -0400 (EDT) Received: from smtpin18.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay02.hostedemail.com (Postfix) with ESMTP id C6EE01206AF for ; Wed, 30 Apr 2025 00:16:44 +0000 (UTC) X-FDA: 83388794328.18.B69BA2C Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) by imf16.hostedemail.com (Postfix) with ESMTP id BF47B18000C for ; Wed, 30 Apr 2025 00:16:42 +0000 (UTC) Authentication-Results: imf16.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=tygRdjHs; dmarc=none; spf=pass (imf16.hostedemail.com: domain of debug@rivosinc.com designates 209.85.214.169 as permitted sender) smtp.mailfrom=debug@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1745972202; a=rsa-sha256; cv=none; b=G/7lHEx+glgUBUrexpwMNAn44kLQijx3v1D/2jsQKEHFy1bcuEMfz9NjIqWd6g5koU1F2M tA6/ur5fDrd1CTeH5OSeT9I4xWGC3TS5P9bnO7uiTMVlKScz2hPxtCqYo9Mi7OAna0DEFb bRALQtQkKpAhwuqehrxRsBqzQHwveb0= ARC-Authentication-Results: i=1; imf16.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=tygRdjHs; dmarc=none; spf=pass (imf16.hostedemail.com: domain of debug@rivosinc.com designates 209.85.214.169 as permitted sender) smtp.mailfrom=debug@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1745972202; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=eyCgE0sNHOlyx9zGD2XlqTc9W1j01DyA5vw9LyX8zMs=; b=TCl804yTcl6wa7gndg26bKXSHFPvIDzqyUc6fLqQeloRiuXCgzsMTI9v+T7cx01FkLAtQi fBZWzUGt8FrWwtOoLNcw8DErhiMrnCEk7cV4vLyCqiA1Q05ROiv5J4WEe1aaqg6Sot0R9Y EnqswDQi3RLou+a0AITdYUgYIBB4UzM= Received: by mail-pl1-f169.google.com with SMTP id d9443c01a7336-2241053582dso99971325ad.1 for ; Tue, 29 Apr 2025 17:16:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1745972202; x=1746577002; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eyCgE0sNHOlyx9zGD2XlqTc9W1j01DyA5vw9LyX8zMs=; b=tygRdjHsN92r7A3M0ccLEuXT8XaJYZrGv8fj7ZyuQYcMIuDJiba0cZuPwst7FVX1mF 3HpogX0mHELaJedOqH+aUXJ2hLTlAkCezp7U0mqAjI6j/XErAuR5XdLNEoLi/l4zsDwI UJqSOhLe3hsM7HadRcIsAc/7piNw/o1yPborJOvzBq9BgU6BaMAJGmA3A0VV21krFw9J 9r/ZFFVcety4v1EkabK+MigKL1YWtZ0oFzSCoanVhu+fVtsHQ1ia0zfVlBxtBP4FAMRy Umv8/EHNf2bRuQNnuf7QXZWUo1dmUSBs5qFqJNxt6lkW110qrAlmav0f83YZF379Uz6T Dttw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745972202; x=1746577002; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eyCgE0sNHOlyx9zGD2XlqTc9W1j01DyA5vw9LyX8zMs=; b=XwSEYy2pi0qV5qTy0pFrTyeVjUmipx4S1jOL24XcaHEd64wqN5udpRO4l0kI1GvwUC 6nfop3t6h3gvmyOH/9guy0iaAY8jGztoACDzcCGHAY78/WYEDqpQplCvY4qF5QHh6VUZ S55Qj1A4BkcPfsmYKhK4ZWylhQNRNZZcAZfHe8RDXg7qcm11boZHBbPM+2rFR3ORRkvq 0aTCQkxEvBfbLA7+XoOohAkLKSLaDFMBgKT9SK54owe5qNwnRGw6YpdWkLISEXl+DhGT pkmI0fMedj/iYgO0K4A1VC82Anrr+yVXBtAQsD4THSEPhaHAC1Ro3v0kZsklNEpQcWnn 6IjQ== X-Forwarded-Encrypted: i=1; AJvYcCXKiPDrbNQJCfL/JED8uIwkSzsnjWIK+asZnMmj6kVZxjoJZcMFYHKeitbo3p+G6uigjLRgHsXBQA==@kvack.org X-Gm-Message-State: AOJu0YxJqBmyi91TALQiu7esSpQfZGAHsJMDj5Fi3LtUfjT/hLbQCLMt DP5biKoVNPA8FZrpuPrNGGiPKPEl4iO9Dv8FpmDTjZg52zLEU5vJLLsmyL+1GgY= X-Gm-Gg: ASbGncthM5clEpv0FsM7ZgxDiiZdNGPCnp5fDRzW6Gm+nlg7vz5t0mix7c/bnTUTJII SjvIqQ5VgliTi5Wa7WL8YyJnhuTv3Nl7kf3QjRHbyL77bg3b0mOgCzoVa6xMkOXkbNn8e+GKa7I MGLeIvOZe5Vm4VBnObk26CPrFMf4ZfUitvnM5I5iE85p+T2R83fObYtdoWwydM5WFzAHUCzrIw/ RuKbgafZDEkyP2W1kvgFIs+T17ZSsksM4SVgA3H8OjAW2VMj9R0jY+m7m00xd6HG80gMgXcaw0W ggY6Y2gLvBR0g+2q3DA8X2k0GDaYm2jfFlGHMt4fFQt2a58+8e8= X-Google-Smtp-Source: AGHT+IHe4GmqH3A4bkQzoQX0kbX9VQ40AhHjKMv6yVTwaVC4Z0lHoaKG8FLcVA+eipUEtZcj/tZgcw== X-Received: by 2002:a17:902:e788:b0:223:5379:5e4e with SMTP id d9443c01a7336-22df5764436mr8015695ad.10.1745972201688; Tue, 29 Apr 2025 17:16:41 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4d770d6sm109386035ad.17.2025.04.29.17.16.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 17:16:41 -0700 (PDT) From: Deepak Gupta Date: Tue, 29 Apr 2025 17:16:22 -0700 Subject: [PATCH v14 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250429-v5_user_cfi_series-v14-5-5239410d012a@rivosinc.com> References: <20250429-v5_user_cfi_series-v14-0-5239410d012a@rivosinc.com> In-Reply-To: <20250429-v5_user_cfi_series-v14-0-5239410d012a@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Zong Li , Deepak Gupta X-Mailer: b4 0.13.0 X-Rspamd-Server: rspam03 X-Rspamd-Queue-Id: BF47B18000C X-Stat-Signature: 6zosyohby471cfbquhasutr5sz5jasns X-Rspam-User: X-HE-Tag: 1745972202-798756 X-HE-Meta: U2FsdGVkX19uLzDMBU7Q+c3m/WXyhWJq6ftzhKAHpOOlMW15gqxwAxUJeUngvdIHusc0Js1UWEPZRMrG+Hn5ook8CdhL4jduuVKJ6mtNiWyB/Lo8BfQD8R7XtBzKR8cKMXnfQMUegjLLa4gKefN29jAQc80bHSl0WU6ZrkXOJiQtFTfQ9hV+HyCRgGVkDd0AV4aJG7w/auU3maXHcEHon+zT4EMYaVVoATC4aljTJm3w+iUjacKVRFcHxDq/b3ZlqvHoyKcOteHXX/ygIpt4IRw4ekzgYxp3tOjS9ApK9ebI8moE3Np6dbFXDbfxWpIC9UUAl5Ps2+Mvwk3bBDKwDdw8XNmEL73IUnYJA2mmICFgt0hvANyPUWvGSu+GkSo83Vhi3d6LUO+4+ApmdhRCzo7s9NJV4sXlU3JMZyuAZOlwYt3gvhG80DszZbsG76IsOnDRqgzT9QqfFAgctMc43ZStmoN8ZQJthoFF/+QPFxsYLYrPiAqsId6D31XrswHNP2R1RSLH7vYnRCa/SJ6+kTt81d/XdizGqqQ7f21U2FESaEc0Le7XOkyoA8bsvrNgpSuH6P6IQucF9a2RVR3vhancwWVuI4u+jMm23QxNHXn6Nx2bq7yuliMIU4bOQS4mJY62nQX5j58LzaTr+Z1c75sZ5Rkss+2DAuK+ppsORD67h5RcEnzVbVJ2M4FfQmIWfps26ycJyHcAVsnlUk+Lm1uHX52hM+qfD8/t0fnunY7S/z1kGgppoELlOmlMX3SuFjV/d+izo2Wffs1H3784RZPmJqsAx6MArbyE8KIKCAUTdseabFAXyrD/qBSzUciuP1LiTfRiN657VcRX2eXM2+HJbZAwZqhfgrgSLO1E/xVTe0kxA9Dd6nXvv+Mor+7/2bhHLvy/8OAKawUyzD+LTUGLMTDShI8tv0CKImtKb+wuFZm08zXXuh0S+jv6N4jnMzzBH35gn2z/cANL5io TzFCaFjp NqNTiNZT6aIAU4zjh8FuoSJLRslP4jxxepJ64+LXuRGRtqi1fULDjMV44MfRBfAnLXGQVXBb0nDKXMcgwd1HUFWQ28KGjcvntIaFUvSrWufb4z7qbtbkHetk6hcrAO4UM08jcN+3c4LVty2ii5kojNWlRIlnbsVvk/M7jmd3ton3pDgr5sTxHGRaZ5AnDvyC9IH9zWR3VhaAXTAMZTG2NmQqAsIBLx2jz3yb+iihoMno+DVXGVXgTj7Mb03q69mBtzvMmKRz+h2fM/n0T36REjpRzXxNGJyRMkeAhxf6IjA1080cIm/NSxhEytxTAiRXPTtVmyJAWU12OesvksirPxmAWsLSFUslOlCRjsTxeDGmCY/+7zAugjkuUJaDh2sVdHj+Q/wneyNIbqnPRz8WUeVdpsJD8qSNqaqk1+TzVQ2ON6X5rBk2SzWhQczQYAL8rs6Pkcx8a4KFAO4TeZ+GpwIhVvGErIl41LA0aKtEWPJfhjGm/ZjpVqn2b5YomICTOgpaJ3G4cCQS1KMCwi6NBG3ObG21rPkTUSce8aU/wxQ6sjw3mK3/D2p/5+w== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Carves out space in arch specific thread struct for cfi status and shadow stack in usermode on riscv. This patch does following - defines a new structure cfi_status with status bit for cfi feature - defines shadow stack pointer, base and size in cfi_status structure - defines offsets to new member fields in thread in asm-offsets.c - Saves and restore shadow stack pointer on trap entry (U --> S) and exit (S --> U) Shadow stack save/restore is gated on feature availiblity and implemented using alternative. CSR can be context switched in `switch_to` as well but soon as kernel shadow stack support gets rolled in, shadow stack pointer will need to be switched at trap entry/exit point (much like `sp`). It can be argued that kernel using shadow stack deployment scenario may not be as prevalant as user mode using this feature. But even if there is some minimal deployment of kernel shadow stack, that means that it needs to be supported. And thus save/restore of shadow stack pointer in entry.S instead of in `switch_to.h`. Reviewed-by: Charlie Jenkins Reviewed-by: Zong Li Reviewed-by: Alexandre Ghiti Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/thread_info.h | 3 +++ arch/riscv/include/asm/usercfi.h | 23 +++++++++++++++++++++++ arch/riscv/kernel/asm-offsets.c | 4 ++++ arch/riscv/kernel/entry.S | 28 ++++++++++++++++++++++++++++ 5 files changed, 59 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index e3aba3336e63..d851bb5c6da0 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -14,6 +14,7 @@ #include #include +#include #define arch_get_mmap_end(addr, len, flags) \ ({ \ diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index f5916a70879a..e066f41176ca 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -73,6 +73,9 @@ struct thread_info { */ unsigned long a0, a1, a2; #endif +#ifdef CONFIG_RISCV_USER_CFI + struct cfi_state user_cfi_state; +#endif }; #ifdef CONFIG_SHADOW_CALL_STACK diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h new file mode 100644 index 000000000000..94b214c295c0 --- /dev/null +++ b/arch/riscv/include/asm/usercfi.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright (C) 2024 Rivos, Inc. + * Deepak Gupta + */ +#ifndef _ASM_RISCV_USERCFI_H +#define _ASM_RISCV_USERCFI_H + +#ifndef __ASSEMBLY__ +#include + +#ifdef CONFIG_RISCV_USER_CFI +struct cfi_state { + unsigned long ubcfi_en : 1; /* Enable for backward cfi. */ + unsigned long user_shdw_stk; /* Current user shadow stack pointer */ + unsigned long shdw_stk_base; /* Base address of shadow stack */ + unsigned long shdw_stk_size; /* size of shadow stack */ +}; + +#endif /* CONFIG_RISCV_USER_CFI */ + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_USERCFI_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index 16490755304e..f33945432f8f 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -49,6 +49,10 @@ void asm_offsets(void) #endif OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); +#ifdef CONFIG_RISCV_USER_CFI + OFFSET(TASK_TI_CFI_STATE, task_struct, thread_info.user_cfi_state); + OFFSET(TASK_TI_USER_SSP, task_struct, thread_info.user_cfi_state.user_shdw_stk); +#endif OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); OFFSET(TASK_THREAD_F1, task_struct, thread.fstate.f[1]); OFFSET(TASK_THREAD_F2, task_struct, thread.fstate.f[2]); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 33a5a9f2a0d4..c4bfe2085c41 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -91,6 +91,32 @@ REG_L a0, TASK_TI_A0(tp) .endm +/* + * If previous mode was U, capture shadow stack pointer and save it away + * Zero CSR_SSP at the same time for sanitization. + */ +.macro save_userssp tmp, status + ALTERNATIVE("nops(4)", + __stringify( \ + andi \tmp, \status, SR_SPP; \ + bnez \tmp, skip_ssp_save; \ + csrrw \tmp, CSR_SSP, x0; \ + REG_S \tmp, TASK_TI_USER_SSP(tp); \ + skip_ssp_save:), + 0, + RISCV_ISA_EXT_ZICFISS, + CONFIG_RISCV_USER_CFI) +.endm + +.macro restore_userssp tmp + ALTERNATIVE("nops(2)", + __stringify( \ + REG_L \tmp, TASK_TI_USER_SSP(tp); \ + csrw CSR_SSP, \tmp), + 0, + RISCV_ISA_EXT_ZICFISS, + CONFIG_RISCV_USER_CFI) +.endm SYM_CODE_START(handle_exception) /* @@ -147,6 +173,7 @@ SYM_CODE_START(handle_exception) REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 + save_userssp s2, s1 csrr s2, CSR_EPC csrr s3, CSR_TVAL csrr s4, CSR_CAUSE @@ -236,6 +263,7 @@ SYM_CODE_START_NOALIGN(ret_from_exception) * structures again. */ csrw CSR_SCRATCH, tp + restore_userssp s3 1: #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE move a0, sp -- 2.43.0