From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6ED32C369DC for ; Wed, 30 Apr 2025 00:25:11 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id BD37E6B00AE; Tue, 29 Apr 2025 20:25:03 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id B5C106B00AF; Tue, 29 Apr 2025 20:25:03 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 8F0646B00B0; Tue, 29 Apr 2025 20:25:03 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0013.hostedemail.com [216.40.44.13]) by kanga.kvack.org (Postfix) with ESMTP id 5A4606B00AE for ; Tue, 29 Apr 2025 20:25:03 -0400 (EDT) Received: from smtpin14.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id C46F18156E for ; Wed, 30 Apr 2025 00:17:29 +0000 (UTC) X-FDA: 83388796218.14.F9CE0B2 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) by imf20.hostedemail.com (Postfix) with ESMTP id D66EF1C0005 for ; Wed, 30 Apr 2025 00:17:27 +0000 (UTC) Authentication-Results: imf20.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=Y7lEipHv; dmarc=none; spf=pass (imf20.hostedemail.com: domain of debug@rivosinc.com designates 209.85.216.45 as permitted sender) smtp.mailfrom=debug@rivosinc.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1745972247; a=rsa-sha256; cv=none; b=WNKsDOFXRb/0+FQV8Fq2JpuZ/hqjBTV7ljCCmA58WihSgSIDQIc+ECo8RFTtzo16tGE+ck cPVV4/yhWZ8SQx28GBMraNOPZ3u2OY0OPzqHRTq8Wx2JdIphgBnF/RvctFKwBgaCTcd1Dr 79nYSbvPNUhsnv5P05WV3nUYayU941o= ARC-Authentication-Results: i=1; imf20.hostedemail.com; dkim=pass header.d=rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=Y7lEipHv; dmarc=none; spf=pass (imf20.hostedemail.com: domain of debug@rivosinc.com designates 209.85.216.45 as permitted sender) smtp.mailfrom=debug@rivosinc.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1745972247; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=Ju4eTa3aeO/W78J21C+hNLwsAKoKH1MKseai5GOrm10=; b=o8JXH5md/yPZTmg9PuDRumkbZYvEz82ZTr3gu1wd/kRIKcdTwJRayBZ/TWgepqT5tWweAc qh6jD/6n6GPDWo39BYWlW7SUkCPitItHaE75M/89OseWDi9MPtWwYAftAZlH2p+dIjHWXs 4ws5NLRnh1bZfeMyl94vPK1BOG8WpTo= Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-301302a328bso9183436a91.2 for ; Tue, 29 Apr 2025 17:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1745972247; x=1746577047; darn=kvack.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ju4eTa3aeO/W78J21C+hNLwsAKoKH1MKseai5GOrm10=; b=Y7lEipHvGLm9pbCDE1CibA6gicGglNOGzKha43hI+WvL15g4qPGCcEDd/4wB3bwTdq cS2A3v+Gk/oeg7w9l+sT1SxUx4p/RtjsZkn4O+Y/RcrVSJtnrK2NfIr4kJV/WJX2tZV7 OC7DzDdGqLge4EyI2HGW/6k3M6Rn6fKJftiuGXonbyODCb0FkOrVwG3aKOfr3CBbJG0W 8OrJ8zmlxo6oetPBtdsmf31ZndrgUNb0lV7BlZBQRNHM+lB8qbYSt29eJ1AKlMNuOGSG 7xClARTrxNeOcy1rf31Ip84RIM+37jV9O7fmSqMxHLBl2uFMyMLdEl/53byAW73hOcUc OipQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745972247; x=1746577047; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ju4eTa3aeO/W78J21C+hNLwsAKoKH1MKseai5GOrm10=; b=EI0o+kn/hHJV4DtK6qNkL3CzGbzycG/zHJDe2xcQHVx8hy4J/lJs+Ji3s0cuhuWDjd NXq18ySv9yumbzK8nMWSfnNiP/Ej7C9nufzcDZmUYdZje2gRi6/e8A8quMaIGlcMP5jD +Uzp/9gAV01r+XjPu57m6QgHf+Ja0b42KEisyw/AkYzU4KQk26+/oPOhQMeulAh6dmN/ mmd1vw93Yld736V3ZkU8CjLhzbeUmn8KyxXMdbjtgozqfKVR4H1pFYfjjUYENTcyiy+E xDxUurKNBrMkRoJ6UGOlbN+SgqVQPNaGszpQH3YDHKWgDyxJuf4lt9o7eCFttlFqaQ/m i7Zw== X-Forwarded-Encrypted: i=1; AJvYcCU9l45Mm1SW2QtohZrGUWjs2vu7YXFbMZo3K0gLvhaJjoa7w2LJQzTA7mGFejiamFHePhe6UKumTA==@kvack.org X-Gm-Message-State: AOJu0YyPOBBq4pd347gfCKOJWE1LRjZMGSD9qrIK/3Z9MHqZFsN/EqbO h1qBbbFfJbk3V6VIFjMR3xyCMrEYSKlgRh/BSvsDLR+luyUaitRejLqXPeHDt98= X-Gm-Gg: ASbGnctFiGgYlszk4Jxoa5KDQrB/vZvGFwJ96tS+ovAraXdH2Km5ERk44OGYK0bEhyh 6ftTmcTStJC0gVQ8PasyJ2OP0ql9Sz6oYo2hK9jS3Q9uDU6CKxown1TrTsudGLqxBn6jmfkolqZ bCg52zUAyjNvCfqnimUD6T++lhuaGrnocGlpPN5wYF/undGIQ2KcEkoF33YUWbT4U3APcWDxdGx MHH9Kixpj9ydPB0rPmUx7kjSuUMDAIyzBz31BI7v1YYs9KNwN453Y88BLDtjZZtKA9f00Kuf3kq E+X8NTchMUw1aB7HPd+8Wf/UBV+ho5k1oonOL5AUt87ayQGRWos= X-Google-Smtp-Source: AGHT+IHH5NBSIb8w2pDY2b1vP5J0WH8G+fGjXta1eAYEaxn/Svks1PLLA3C2BoMoZknQ17FEY5W4rQ== X-Received: by 2002:a17:90b:4fc2:b0:2fe:a545:4c85 with SMTP id 98e67ed59e1d1-30a33354fc9mr1556226a91.27.1745972246632; Tue, 29 Apr 2025 17:17:26 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4d770d6sm109386035ad.17.2025.04.29.17.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Apr 2025 17:17:26 -0700 (PDT) From: Deepak Gupta Date: Tue, 29 Apr 2025 17:16:36 -0700 Subject: [PATCH v14 19/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250429-v5_user_cfi_series-v14-19-5239410d012a@rivosinc.com> References: <20250429-v5_user_cfi_series-v14-0-5239410d012a@rivosinc.com> In-Reply-To: <20250429-v5_user_cfi_series-v14-0-5239410d012a@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Deepak Gupta X-Mailer: b4 0.13.0 X-Rspamd-Queue-Id: D66EF1C0005 X-Stat-Signature: nnnrocarmx3gf3pzh697fpb1361d4qir X-Rspam-User: X-Rspamd-Server: rspam08 X-HE-Tag: 1745972247-345802 X-HE-Meta: U2FsdGVkX18rwfYbZAIWYwBosg8FDFI7dI0GF3JKr5QQo/TYOFCU7kDbPJdJgzH6T115pLyZn/ETSsgTnvO8seWc+OjMB3ZkNPlKd3CSCAuk3EdR1JoQigG68ALmbsx8Iq6q2LWciaLn45clMsfpWjreElikn6RJEFP//jGGwuB6MGLcIuHHJeu015qM7V9b4pXde3/ArOXtNwrGQEaNQaOquZjAysH7DF5sfsLe6OI8Fx3+3PgsrkD9yGxr0PWPPyvQHoZDbtUDuwWjwA8dO+CZZmmBeNrS9P1I1xnxEqttHcRD0JyO2GIO33hxMeTgAKM9Wnp4laDvn9WGTJVAeMjBzYV1FLo1lI9dyT5Rku9MxH3zRSka7VgF/W+2UsDHgK4/IIL3jLqiwpjyzwbojbDrIrR/BINEfl/poI5a9ooLaSrh/EQeASQfVrxMmJE426YnpoM9bB5s/O7+yfnXHQI3wL3YpcIbmj7kC3BKQAB2vbEnclmRCPIcgLatg+FoT0oGfoSjlBjTOfz/DI4AEFCUAbM6k/lDX/zMz8u+9mGoQDj6KD/JRFR5vxiE82iv3fp1MUJd/5Hwv5+mj6KALxOzfsIGtGlkIEgxcdBAjnPxZzVZwuVpVIqCTQnyAV4auuZ4UitlkZazLRwuSpS5+ykddR7HlTHrx1+13U6slHJhBTcy+O7EaubvQPkkxyd2sXIbs0q+7VVD6TrfRtJJdLuJQrVjzWHK48MNEeC3LtC9OgAI0ZMfcbtUODV1tsG4IEz+oWyi+zbWXDqPlPxM7HtPv8rblTWj8EmeP6Vq0dil13Y/tOLOyOoqSN6UfV6Q9gFdfOb6U5zkGQvNsVGZCyD/OAUUdwJneTws5LGkF5xJm1gXuydoNpIRKA/DlqjUI9h5cwoKCXdeV+3zklk3oykAA49rqNwiZ7o+LH7hSi0FaD5gDMg8k/k0zAYu8MiAblDzzJ1zq9uVSDTFarR LueyulGQ /2r7X1To+Yo2BVew37Xm2sqBXBFZqU/1wer2HIJ/5JHGrLaqE1me/vEZsRD8mzYF0/ertvUS1Q3hwi3bfpsTWdDbTFO5CTjutyi19qk9d56ppwqT9RuXbowMkkUQYLUAs+mYkCWIWQ3u8G6ueJBVeTCLdJCttmFoNi6cDzjL5hMFl5xiQC186EFc79ecegXSXt4XFAmZHpnm+v3q4iSKLxU5wzQcV1+rSdNp8twv5ekAHcRbCMOFQw6zV8JTqeYz3xBDhizMEHMdj1k6RSLcTBGoasK6cCV4v0lOfXCD8HmjssXWc4Vb7ijfsoRQisyyYiDVpqBqyfgO8JIkLsg5Zd0T1PJ1AXw+aMEF0cv3o5B0P9Q6fuJjvoqbnuu9j6ls20yZqZ3YMnEKMljBSUpWyvgmvvZfrQ4RKQ51ocgZ5vO7AJ/9jyOboaMXFo4//dQisupqDrMau45hJy6A= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling, disabling and locking of feature is not allowed via ptrace set interface. However setting `elp` state or setting shadow stack pointer are allowed via ptrace set interface . It is expected `gdb` might have use to fixup `elp` state or `shadow stack` pointer. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/ptrace.h | 30 ++++++++++++ arch/riscv/kernel/ptrace.c | 95 ++++++++++++++++++++++++++++++++++++ include/uapi/linux/elf.h | 2 + 3 files changed, 127 insertions(+) diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h index 659ea3af5680..42c3fc8bd513 100644 --- a/arch/riscv/include/uapi/asm/ptrace.h +++ b/arch/riscv/include/uapi/asm/ptrace.h @@ -131,6 +131,36 @@ struct __sc_riscv_cfi_state { unsigned long ss_ptr; /* shadow stack pointer */ }; +#define PTRACE_CFI_LP_EN_BIT 0 +#define PTRACE_CFI_LP_LOCK_BIT 1 +#define PTRACE_CFI_ELP_BIT 2 +#define PTRACE_CFI_SS_EN_BIT 3 +#define PTRACE_CFI_SS_LOCK_BIT 4 +#define PTRACE_CFI_SS_PTR_BIT 5 + +#define PTRACE_CFI_LP_EN_STATE (1 << PTRACE_CFI_LP_EN_BIT) +#define PTRACE_CFI_LP_LOCK_STATE (1 << PTRACE_CFI_LP_LOCK_BIT) +#define PTRACE_CFI_ELP_STATE (1 << PTRACE_CFI_ELP_BIT) +#define PTRACE_CFI_SS_EN_STATE (1 << PTRACE_CFI_SS_EN_BIT) +#define PTRACE_CFI_SS_LOCK_STATE (1 << PTRACE_CFI_SS_LOCK_BIT) +#define PTRACE_CFI_SS_PTR_STATE (1 << PTRACE_CFI_SS_PTR_BIT) + +#define PRACE_CFI_STATE_INVALID_MASK ~(PTRACE_CFI_LP_EN_STATE | \ + PTRACE_CFI_LP_LOCK_STATE | \ + PTRACE_CFI_ELP_STATE | \ + PTRACE_CFI_SS_EN_STATE | \ + PTRACE_CFI_SS_LOCK_STATE | \ + PTRACE_CFI_SS_PTR_STATE) + +struct __cfi_status { + __u64 cfi_state; +}; + +struct user_cfi_state { + struct __cfi_status cfi_status; + __u64 shstk_ptr; +}; + #endif /* __ASSEMBLY__ */ #endif /* _UAPI_ASM_RISCV_PTRACE_H */ diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c index ea67e9fb7a58..933a3d26d33c 100644 --- a/arch/riscv/kernel/ptrace.c +++ b/arch/riscv/kernel/ptrace.c @@ -19,6 +19,7 @@ #include #include #include +#include enum riscv_regset { REGSET_X, @@ -31,6 +32,9 @@ enum riscv_regset { #ifdef CONFIG_RISCV_ISA_SUPM REGSET_TAGGED_ADDR_CTRL, #endif +#ifdef CONFIG_RISCV_USER_CFI + REGSET_CFI, +#endif }; static int riscv_gpr_get(struct task_struct *target, @@ -184,6 +188,87 @@ static int tagged_addr_ctrl_set(struct task_struct *target, } #endif +#ifdef CONFIG_RISCV_USER_CFI +static int riscv_cfi_get(struct task_struct *target, + const struct user_regset *regset, + struct membuf to) +{ + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + memset(&user_cfi, 0, sizeof(user_cfi)); + regs = task_pt_regs(target); + + if (is_indir_lp_enabled(target)) { + user_cfi.cfi_status.cfi_state |= PTRACE_CFI_LP_EN_STATE; + user_cfi.cfi_status.cfi_state |= is_indir_lp_locked(target) ? + PTRACE_CFI_LP_LOCK_STATE : 0; + user_cfi.cfi_status.cfi_state |= (regs->status & SR_ELP) ? + PTRACE_CFI_ELP_STATE : 0; + } + + if (is_shstk_enabled(target)) { + user_cfi.cfi_status.cfi_state |= (PTRACE_CFI_SS_EN_STATE | + PTRACE_CFI_SS_PTR_STATE); + user_cfi.cfi_status.cfi_state |= is_shstk_locked(target) ? + PTRACE_CFI_SS_LOCK_STATE : 0; + user_cfi.shstk_ptr = get_active_shstk(target); + } + + return membuf_write(&to, &user_cfi, sizeof(user_cfi)); +} + +/* + * Does it make sense to allowing enable / disable of cfi via ptrace? + * Not allowing enable / disable / locking control via ptrace for now. + * Setting shadow stack pointer is allowed. GDB might use it to unwind or + * some other fixup. Similarly gdb might want to suppress elp and may want + * to reset elp state. + */ +static int riscv_cfi_set(struct task_struct *target, + const struct user_regset *regset, + unsigned int pos, unsigned int count, + const void *kbuf, const void __user *ubuf) +{ + int ret; + struct user_cfi_state user_cfi; + struct pt_regs *regs; + + regs = task_pt_regs(target); + + ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &user_cfi, 0, -1); + if (ret) + return ret; + + /* + * Not allowing enabling or locking shadow stack or landing pad + * There is no disabling of shadow stack or landing pad via ptrace + * rsvd field should be set to zero so that if those fields are needed in future + */ + if ((user_cfi.cfi_status.cfi_state & + (PTRACE_CFI_LP_EN_STATE | PTRACE_CFI_LP_LOCK_STATE | + PTRACE_CFI_SS_EN_STATE | PTRACE_CFI_SS_LOCK_STATE)) || + (user_cfi.cfi_status.cfi_state & PRACE_CFI_STATE_INVALID_MASK)) + return -EINVAL; + + /* If lpad is enabled on target and ptrace requests to set / clear elp, do that */ + if (is_indir_lp_enabled(target)) { + if (user_cfi.cfi_status.cfi_state & + PTRACE_CFI_ELP_STATE) /* set elp state */ + regs->status |= SR_ELP; + else + regs->status &= ~SR_ELP; /* clear elp state */ + } + + /* If shadow stack enabled on target, set new shadow stack pointer */ + if (is_shstk_enabled(target) && + (user_cfi.cfi_status.cfi_state & PTRACE_CFI_SS_PTR_STATE)) + set_active_shstk(target, user_cfi.shstk_ptr); + + return 0; +} +#endif + static const struct user_regset riscv_user_regset[] = { [REGSET_X] = { .core_note_type = NT_PRSTATUS, @@ -224,6 +309,16 @@ static const struct user_regset riscv_user_regset[] = { .set = tagged_addr_ctrl_set, }, #endif +#ifdef CONFIG_RISCV_USER_CFI + [REGSET_CFI] = { + .core_note_type = NT_RISCV_USER_CFI, + .align = sizeof(__u64), + .n = sizeof(struct user_cfi_state) / sizeof(__u64), + .size = sizeof(__u64), + .regset_get = riscv_cfi_get, + .set = riscv_cfi_set, + }, +#endif }; static const struct user_regset_view riscv_user_native_view = { diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h index 819ded2d39de..ee30dcd80901 100644 --- a/include/uapi/linux/elf.h +++ b/include/uapi/linux/elf.h @@ -545,6 +545,8 @@ typedef struct elf64_shdr { #define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */ #define NN_RISCV_TAGGED_ADDR_CTRL "LINUX" #define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */ +#define NN_RISCV_USER_CFI "LINUX" +#define NT_RISCV_USER_CFI 0x903 /* RISC-V shadow stack state */ #define NN_LOONGARCH_CPUCFG "LINUX" #define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */ #define NN_LOONGARCH_CSR "LINUX" -- 2.43.0