From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67C72C369C2 for ; Tue, 22 Apr 2025 22:10:14 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id A35D76B000A; Tue, 22 Apr 2025 18:10:08 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 9C3B16B000C; Tue, 22 Apr 2025 18:10:08 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 6613D6B000D; Tue, 22 Apr 2025 18:10:08 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 413C26B000A for ; Tue, 22 Apr 2025 18:10:08 -0400 (EDT) Received: from smtpin12.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay09.hostedemail.com (Postfix) with ESMTP id 815A681F5E for ; Tue, 22 Apr 2025 22:10:08 +0000 (UTC) X-FDA: 83363073696.12.3C76E69 Received: from mail-io1-f99.google.com (mail-io1-f99.google.com [209.85.166.99]) by imf19.hostedemail.com (Postfix) with ESMTP id 721D91A0003 for ; Tue, 22 Apr 2025 22:10:06 +0000 (UTC) Authentication-Results: imf19.hostedemail.com; dkim=pass header.d=purestorage.com header.s=google2022 header.b=ay7mkbaC; dmarc=pass (policy=reject) header.from=purestorage.com; spf=pass (imf19.hostedemail.com: domain of csander@purestorage.com designates 209.85.166.99 as permitted sender) smtp.mailfrom=csander@purestorage.com ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1745359806; a=rsa-sha256; cv=none; b=LcGKG4DI0a4tQvdWPzwa/Ykd620dPTAphnGeK5yBD+TFKqD8PK+14O1KCki7f1RpS/QMop nOTeTWxIPDALAvdUydKKYH2Y+0fvwRrkKmVczL6mhIMoFpkQjhUQTco4xr5yGl8PJpU/Tt M6NKCSxFu5hXUDlhXCm7BEzw5zTNvLQ= ARC-Authentication-Results: i=1; imf19.hostedemail.com; dkim=pass header.d=purestorage.com header.s=google2022 header.b=ay7mkbaC; dmarc=pass (policy=reject) header.from=purestorage.com; spf=pass (imf19.hostedemail.com: domain of csander@purestorage.com designates 209.85.166.99 as permitted sender) smtp.mailfrom=csander@purestorage.com ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1745359806; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references:dkim-signature; bh=++esc3uXgAvfAB+lpuA22G1/oTR1JRPmWb67bwlXmoA=; b=dqHk4s8Ri5FZJkdnlNRqo0WuTlsSkKT3ic6urJNkWZn1d+lATWTxjh9wn0Lv4ktvNzbFoq CzzY14sbNRwtGz/hhqkmlJ+Z5xz+WOABnHTxJOIxip6/x6Y41XGAvIexW2OGjB/r2g4mYT iGHxm384rtm5ofL00mKQdFiNxFUKcLI= Received: by mail-io1-f99.google.com with SMTP id ca18e2360f4ac-85b418faf5cso14187439f.3 for ; Tue, 22 Apr 2025 15:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=purestorage.com; s=google2022; t=1745359805; x=1745964605; darn=kvack.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=++esc3uXgAvfAB+lpuA22G1/oTR1JRPmWb67bwlXmoA=; b=ay7mkbaCFaZy4sivgm/RVrd4bPxnO1vIFuYKbRyAVc0yKZmrk6mxdHYe4Ft0eSJ/sj JkTW3U/0C2a9drmJgU4czdJvwdoMt+WSlU2a1HRTZoXL2FGCJDUO3Ka5IGO5SxH9HhGP U7VQ1fsBvaJYMORKCcomCgu6Tj1CCq8qzQXhLjgc3dy5koLCYKShnvJ1+/1WPwZw2Z/W DH+gp91dpjgL3K8Jelyp/V5f8mnI3d56ZlPNOT5rby6jmS/pHUi78HAuVAzKjtQI9ftQ Eh2rJL/98g8oTF494LTGRorui1dJQC0axX+0PvybuK2I99/iRKnYfiW1S+Nj9Xi4S7cw 8kBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745359805; x=1745964605; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=++esc3uXgAvfAB+lpuA22G1/oTR1JRPmWb67bwlXmoA=; b=KSkLGvVl8T7V5kt51fGxqIA8ejJ692KqUrX7ls20B1zY715NP501lnx03E9yHvr+4Y xvNJSzyu2RecSsgGrVWM3JX9m+WeXAm91BUhKp6NB21ECHqDOoyZ+Ln87YUyPLpRiBZU /BsEBBg3ZhkAtq1jSVs35Fh+bI8uX/rYsEBSfry3TbpbEsO+x0Rubc8LezBSwoBJo00h Lq6C9vXEKyIM1EfleFG+/TEp2UHaZzSb0AW3w19Ox5QB7kJB74RIrRPGAH/yoivkL066 nbHYL3o/iNaueO9v7piMgJgeeocb/54nZvayDHb0fcqz6ETy1bEmL/v+MWwqBjwH4MRR /uTA== X-Forwarded-Encrypted: i=1; AJvYcCVK/PpMBndO/okB6S5LbqOLA1YfNUX8jWjT1TDlHvzzL47xhhfo8l5kUp+BlVsekZUVIbmUAGD9YQ==@kvack.org X-Gm-Message-State: AOJu0YzMOq3vyH1iVrTJRcJij1FpqRPLKjH3KIcsA8OdY+p/wZQgfZO2 jtfgqwr5r8kY9KEpPl5wt3sEHpDc9lUmKPu7ksEXjgAvNP6ITrOVxH1hvB0kGb8CbeZKMG8nnUq Tey+rtw+H07RpqrZ3AEN/UeGLjFk4bxRT/j/2QZQkx8d5oYvr X-Gm-Gg: ASbGnctTQpxr1YpCNsEKUbERDcleHw8olYvtki9JOd/RwHU2A0LJ83IUYxo3dg0IpIH +a+yF7XYnadnuXumDvwnnuk6nbeWKg2JTxHd9lN1CRwPyPJKFl5eyD3SpCAXU3C5AXOPCDkJ7kG wBa08vo4QmRUw/Tvg33hBVguX3R9MMQWAvpLSrwQE/BDUKl+bbVotXMZsGJ78Q9gXKdIV5G7zLD WbkBsl9UYPVCOvLs/+yeDzHnLNsCQSzrfA2DfyEVyWbUylnOvYRu06YLrxmq3xa+ZhMLCycrHe0 HrlGFP3zikbb9REfcLU1Ym/Z9nqU0w== X-Google-Smtp-Source: AGHT+IFWOB8MGwiyr92rLomhRhd1eT0wZqfcwwCPR8ekz6+L8OmLpyi7tnN7ap9fq8/HJzc34IggmybJsqBi X-Received: by 2002:a05:6e02:154e:b0:3d9:207f:658c with SMTP id e9e14a558f8ab-3d927107f64mr2986925ab.0.1745359805346; Tue, 22 Apr 2025 15:10:05 -0700 (PDT) Received: from c7-smtp-2023.dev.purestorage.com ([2620:125:9017:12:36:3:5:0]) by smtp-relay.gmail.com with ESMTPS id e9e14a558f8ab-3d92758f997sm164245ab.5.2025.04.22.15.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Apr 2025 15:10:05 -0700 (PDT) X-Relaying-Domain: purestorage.com Received: from dev-csander.dev.purestorage.com (unknown [IPv6:2620:125:9007:640:ffff::418a]) by c7-smtp-2023.dev.purestorage.com (Postfix) with ESMTP id 0829B34045E; Tue, 22 Apr 2025 16:10:05 -0600 (MDT) Received: by dev-csander.dev.purestorage.com (Postfix, from userid 1557716354) id 05CDFE41D69; Tue, 22 Apr 2025 16:10:05 -0600 (MDT) From: Caleb Sander Mateos To: Keith Busch , Jens Axboe , Christoph Hellwig , Sagi Grimberg , Andrew Morton Cc: Kanchan Joshi , linux-nvme@lists.infradead.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Caleb Sander Mateos Subject: [PATCH v5 3/3] nvme/pci: make PRP list DMA pools per-NUMA-node Date: Tue, 22 Apr 2025 16:09:52 -0600 Message-ID: <20250422220952.2111584-4-csander@purestorage.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250422220952.2111584-1-csander@purestorage.com> References: <20250422220952.2111584-1-csander@purestorage.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspamd-Server: rspam11 X-Rspamd-Queue-Id: 721D91A0003 X-Stat-Signature: wd5fpcqieptkxptthorhqmnhz9skrq8o X-Rspam-User: X-HE-Tag: 1745359806-176412 X-HE-Meta: U2FsdGVkX1+mtbzoyt47pMuJHl9Xxxf1fuFnn+KL/gCM+pSj0+VBnosQFR64UXOx6cFkT6YJFwsujFhKuc3l/rEYvPTtCHKBwo0c1Jc1xkgC5FgCWDXvghQvp3H3IDQTT8VPp9Wgo8U6wVn18tP93RYGnkhEWjtWVxTIylmTNSxo3QT+EQOs3icMNMWPJgjeLwJ51Y0HIfk3DC4lJ29ibnWQ71rSslagvf0T1wJTBKGRBBJG1/TkSrwby6LRZ6Kkgh4jn51uTcOI5EQJQ0ibs07W8sJyAJ2GEcuITcC6mXZml3ym8t1LsmVoIuDZn9VpFMrvOqOLbQHsMD2Eae9QMSfdMZz3pjRxysPS4pYEqPEOti4wipHmwiJaA3Ougg+iUE6TyffjUJP8gGjCbRwy66zb11ajWFwpUduJP+RATZcIIzts/Yd+YkqblE1WtNOzudDGX8cLXC2k25mhQqvYLhco6BM5b4fGFXZbYzM8Uhb+g7cseoTv599RMECcmRxzJrrSsPWfBpEo0anNfS5EE7/n01LNPtv46BPqomWtNz6ir2xY5jtaijvhdJRCRoctLveP8YCmRW1oaSHIEftqOVi07OfBzwsNiJGbU/gkGnAe6KNFT692upOtiwR1PK6Oc1NCOuLD1TfyqIfhqxKd6ZRfNQSXtFLxU/4IJl3PoIIKnkLaKq1B0cCvcR+oewH6/A0/G8s2U3L1Bo8yHpoQ8KuLmyKwsZDnMzROyJXdh77uxMC5tI4A5JoZcWK9bxgACoPUsR5j/Mhcc1YVVKGbTNSuf3apJpK5SWimxUT/o1e2SUMrCr6ij64bKKprq0t5sCy7ysxenaTUGb+mq2B75BFo6dSjtcMEUa8ubdBVn2NVhKPA9diZ4d8eMlZZzWmyawpeHDwY9W36gSb6BLtO5AF07L1/BS3gb3chPlN7qVT8p7E1LcqzZLPzja04bRCoA18kgiuGFre4iv/q41K Fh14olQo DxqnAA8WFA8zbkfIVxZduuL2lWQ+H1gulng8ZCTvC6l67cYOzRyNiftMKJic7FqtSvvCwOh0tLW2O0h9FK5Cy2OwtTK6WNWjFkyUwbyD+gSUDvQ+6RhxEMg6iMnPRkpGoL03heKWGrtLwmyxc85BVQ/4gWWJyFI8Bcxep0DlHYWqEDiMsiT9nh0DzLXxdrRT8zQgCn8tFVfgYDm09RVe1tXroCanlKcy/qK9JetQwIhjhCPGUF0YWZN15kfKf4LAR2bUl3/3HpLd0542VNzS1jGz41C0sfJqprI5QLGp1BDsTRN9eb2W+8oPoPK3SiyJAZkF388Cg/dVoBhJlbnLDW3+/wvSVS2EYurfnkxS+h1mx5BZUSn0YGvoZp9oLAA26aoz/yFojEYkCvCl1qO26/NxzZ/iaPOhjqkKrKsC6TcFPNK8= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: NVMe commands with more than 4 KB of data allocate PRP list pages from the per-nvme_device dma_pool prp_page_pool or prp_small_pool. Each call to dma_pool_alloc() and dma_pool_free() takes the per-dma_pool spinlock. These device-global spinlocks are a significant source of contention when many CPUs are submitting to the same NVMe devices. On a workload issuing 32 KB reads from 16 CPUs (8 hypertwin pairs) across 2 NUMA nodes to 23 NVMe devices, we observed 2.4% of CPU time spent in _raw_spin_lock_irqsave called from dma_pool_alloc and dma_pool_free. Ideally, the dma_pools would be per-hctx to minimize contention. But that could impose considerable resource costs in a system with many NVMe devices and CPUs. As a compromise, allocate per-NUMA-node PRP list DMA pools. Map each nvme_queue to the set of DMA pools corresponding to its device and its hctx's NUMA node. This reduces the _raw_spin_lock_irqsave overhead by about half, to 1.2%. Preventing the sharing of PRP list pages across NUMA nodes also makes them cheaper to initialize. Link: https://lore.kernel.org/linux-nvme/CADUfDZqa=OOTtTTznXRDmBQo1WrFcDw1hBA7XwM7hzJ-hpckcA@mail.gmail.com/T/#u Signed-off-by: Caleb Sander Mateos Reviewed-by: Kanchan Joshi Reviewed-by: Sagi Grimberg Reviewed-by: Keith Busch --- drivers/nvme/host/pci.c | 144 +++++++++++++++++++++++----------------- 1 file changed, 84 insertions(+), 60 deletions(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 642890ddada5..2c554bb7f984 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -16,10 +16,11 @@ #include #include #include #include #include +#include #include #include #include #include #include @@ -110,21 +111,24 @@ struct nvme_queue; static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); static void nvme_delete_io_queues(struct nvme_dev *dev); static void nvme_update_attrs(struct nvme_dev *dev); +struct nvme_prp_dma_pools { + struct dma_pool *large; + struct dma_pool *small; +}; + /* * Represents an NVM Express device. Each nvme_dev is a PCI function. */ struct nvme_dev { struct nvme_queue *queues; struct blk_mq_tag_set tagset; struct blk_mq_tag_set admin_tagset; u32 __iomem *dbs; struct device *dev; - struct dma_pool *prp_page_pool; - struct dma_pool *prp_small_pool; unsigned online_queues; unsigned max_qid; unsigned io_queues[HCTX_MAX_TYPES]; unsigned int num_vecs; u32 q_depth; @@ -160,10 +164,11 @@ struct nvme_dev { struct nvme_host_mem_buf_desc *host_mem_descs; void **host_mem_desc_bufs; unsigned int nr_allocated_queues; unsigned int nr_write_queues; unsigned int nr_poll_queues; + struct nvme_prp_dma_pools prp_pools[]; }; static int io_queue_depth_set(const char *val, const struct kernel_param *kp) { return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, @@ -189,10 +194,11 @@ static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) * An NVM Express queue. Each device has at least two (one for admin * commands and one for I/O commands). */ struct nvme_queue { struct nvme_dev *dev; + struct nvme_prp_dma_pools prp_pools; spinlock_t sq_lock; void *sq_cmds; /* only used for poll queues: */ spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; struct nvme_completion *cqes; @@ -395,18 +401,67 @@ static int nvme_pci_npages_prp(void) unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); } +static struct nvme_prp_dma_pools * +nvme_setup_prp_pools(struct nvme_dev *dev, unsigned numa_node) +{ + struct nvme_prp_dma_pools *prp_pools = &dev->prp_pools[numa_node]; + size_t small_align = 256; + + if (prp_pools->small) + return prp_pools; /* already initialized */ + + prp_pools->large = dma_pool_create_node("prp list page", dev->dev, + NVME_CTRL_PAGE_SIZE, + NVME_CTRL_PAGE_SIZE, 0, + numa_node); + if (!prp_pools->large) + return ERR_PTR(-ENOMEM); + + if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512) + small_align = 512; + + /* Optimisation for I/Os between 4k and 128k */ + prp_pools->small = dma_pool_create_node("prp list 256", dev->dev, + 256, small_align, 0, numa_node); + if (!prp_pools->small) { + dma_pool_destroy(prp_pools->large); + prp_pools->large = NULL; + return ERR_PTR(-ENOMEM); + } + + return prp_pools; +} + +static void nvme_release_prp_pools(struct nvme_dev *dev) +{ + unsigned i; + + for (i = 0; i < nr_node_ids; i++) { + struct nvme_prp_dma_pools *prp_pools = &dev->prp_pools[i]; + + dma_pool_destroy(prp_pools->large); + dma_pool_destroy(prp_pools->small); + } +} + static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, unsigned qid) { struct nvme_dev *dev = to_nvme_dev(data); struct nvme_queue *nvmeq = &dev->queues[qid]; + struct nvme_prp_dma_pools *prp_pools; struct blk_mq_tags *tags; tags = qid ? dev->tagset.tags[qid - 1] : dev->admin_tagset.tags[0]; WARN_ON(tags != hctx->tags); + prp_pools = nvme_setup_prp_pools(dev, hctx->numa_node); + if (IS_ERR(prp_pools)) + return PTR_ERR(prp_pools); + + nvmeq->prp_pools = *prp_pools; hctx->driver_data = nvmeq; return 0; } static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, @@ -536,27 +591,28 @@ static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req, if (!sgl_threshold || avg_seg_size < sgl_threshold) return nvme_req(req)->flags & NVME_REQ_USERCMD; return true; } -static void nvme_free_prps(struct nvme_dev *dev, struct request *req) +static void nvme_free_prps(struct nvme_queue *nvmeq, struct request *req) { const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; struct nvme_iod *iod = blk_mq_rq_to_pdu(req); dma_addr_t dma_addr = iod->first_dma; int i; for (i = 0; i < iod->nr_allocations; i++) { __le64 *prp_list = iod->list[i].prp_list; dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); - dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); + dma_pool_free(nvmeq->prp_pools.large, prp_list, dma_addr); dma_addr = next_dma_addr; } } -static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) +static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_queue *nvmeq, + struct request *req) { struct nvme_iod *iod = blk_mq_rq_to_pdu(req); if (iod->dma_len) { dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, @@ -567,17 +623,17 @@ static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) WARN_ON_ONCE(!iod->sgt.nents); dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); if (iod->nr_allocations == 0) - dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, + dma_pool_free(nvmeq->prp_pools.small, iod->list[0].sg_list, iod->first_dma); else if (iod->nr_allocations == 1) - dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, + dma_pool_free(nvmeq->prp_pools.large, iod->list[0].sg_list, iod->first_dma); else - nvme_free_prps(dev, req); + nvme_free_prps(nvmeq, req); mempool_free(iod->sgt.sgl, dev->iod_mempool); } static void nvme_print_sgl(struct scatterlist *sgl, int nents) { @@ -591,11 +647,11 @@ static void nvme_print_sgl(struct scatterlist *sgl, int nents) i, &phys, sg->offset, sg->length, &sg_dma_address(sg), sg_dma_len(sg)); } } -static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, +static blk_status_t nvme_pci_setup_prps(struct nvme_queue *nvmeq, struct request *req, struct nvme_rw_command *cmnd) { struct nvme_iod *iod = blk_mq_rq_to_pdu(req); struct dma_pool *pool; int length = blk_rq_payload_bytes(req); @@ -627,14 +683,14 @@ static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, goto done; } nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); if (nprps <= (256 / 8)) { - pool = dev->prp_small_pool; + pool = nvmeq->prp_pools.small; iod->nr_allocations = 0; } else { - pool = dev->prp_page_pool; + pool = nvmeq->prp_pools.large; iod->nr_allocations = 1; } prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); if (!prp_list) { @@ -672,11 +728,11 @@ static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, done: cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); return BLK_STS_OK; free_prps: - nvme_free_prps(dev, req); + nvme_free_prps(nvmeq, req); return BLK_STS_RESOURCE; bad_sgl: WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), "Invalid SGL for payload:%d nents:%d\n", blk_rq_payload_bytes(req), iod->sgt.nents); @@ -697,11 +753,11 @@ static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, sge->addr = cpu_to_le64(dma_addr); sge->length = cpu_to_le32(entries * sizeof(*sge)); sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; } -static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, +static blk_status_t nvme_pci_setup_sgls(struct nvme_queue *nvmeq, struct request *req, struct nvme_rw_command *cmd) { struct nvme_iod *iod = blk_mq_rq_to_pdu(req); struct dma_pool *pool; struct nvme_sgl_desc *sg_list; @@ -717,14 +773,14 @@ static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); return BLK_STS_OK; } if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { - pool = dev->prp_small_pool; + pool = nvmeq->prp_pools.small; iod->nr_allocations = 0; } else { - pool = dev->prp_page_pool; + pool = nvmeq->prp_pools.large; iod->nr_allocations = 1; } sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); if (!sg_list) { @@ -784,16 +840,16 @@ static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, } static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, struct nvme_command *cmnd) { + struct nvme_queue *nvmeq = req->mq_hctx->driver_data; struct nvme_iod *iod = blk_mq_rq_to_pdu(req); blk_status_t ret = BLK_STS_RESOURCE; int rc; if (blk_rq_nr_phys_segments(req) == 1) { - struct nvme_queue *nvmeq = req->mq_hctx->driver_data; struct bio_vec bv = req_bvec(req); if (!is_pci_p2pdma_page(bv.bv_page)) { if (!nvme_pci_metadata_use_sgls(dev, req) && (bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) + @@ -824,13 +880,13 @@ static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, ret = BLK_STS_TARGET; goto out_free_sg; } if (nvme_pci_use_sgls(dev, req, iod->sgt.nents)) - ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); + ret = nvme_pci_setup_sgls(nvmeq, req, &cmnd->rw); else - ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); + ret = nvme_pci_setup_prps(nvmeq, req, &cmnd->rw); if (ret != BLK_STS_OK) goto out_unmap_sg; return BLK_STS_OK; out_unmap_sg: @@ -841,10 +897,11 @@ static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, } static blk_status_t nvme_pci_setup_meta_sgls(struct nvme_dev *dev, struct request *req) { + struct nvme_queue *nvmeq = req->mq_hctx->driver_data; struct nvme_iod *iod = blk_mq_rq_to_pdu(req); struct nvme_rw_command *cmnd = &iod->cmd.rw; struct nvme_sgl_desc *sg_list; struct scatterlist *sgl, *sg; unsigned int entries; @@ -864,11 +921,11 @@ static blk_status_t nvme_pci_setup_meta_sgls(struct nvme_dev *dev, rc = dma_map_sgtable(dev->dev, &iod->meta_sgt, rq_dma_dir(req), DMA_ATTR_NO_WARN); if (rc) goto out_free_sg; - sg_list = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC, &sgl_dma); + sg_list = dma_pool_alloc(nvmeq->prp_pools.small, GFP_ATOMIC, &sgl_dma); if (!sg_list) goto out_unmap_sg; entries = iod->meta_sgt.nents; iod->meta_list.sg_list = sg_list; @@ -946,11 +1003,11 @@ static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) nvme_start_request(req); return BLK_STS_OK; out_unmap_data: if (blk_rq_nr_phys_segments(req)) - nvme_unmap_data(dev, req); + nvme_unmap_data(dev, req->mq_hctx->driver_data, req); out_free_cmd: nvme_cleanup_cmd(req); return ret; } @@ -1036,10 +1093,11 @@ static void nvme_queue_rqs(struct rq_list *rqlist) nvme_submit_cmds(nvmeq, &submit_list); *rqlist = requeue_list; } static __always_inline void nvme_unmap_metadata(struct nvme_dev *dev, + struct nvme_queue *nvmeq, struct request *req) { struct nvme_iod *iod = blk_mq_rq_to_pdu(req); if (!iod->meta_sgt.nents) { @@ -1047,11 +1105,11 @@ static __always_inline void nvme_unmap_metadata(struct nvme_dev *dev, rq_integrity_vec(req).bv_len, rq_dma_dir(req)); return; } - dma_pool_free(dev->prp_small_pool, iod->meta_list.sg_list, + dma_pool_free(nvmeq->prp_pools.small, iod->meta_list.sg_list, iod->meta_dma); dma_unmap_sgtable(dev->dev, &iod->meta_sgt, rq_dma_dir(req), 0); mempool_free(iod->meta_sgt.sgl, dev->iod_meta_mempool); } @@ -1059,14 +1117,14 @@ static __always_inline void nvme_pci_unmap_rq(struct request *req) { struct nvme_queue *nvmeq = req->mq_hctx->driver_data; struct nvme_dev *dev = nvmeq->dev; if (blk_integrity_rq(req)) - nvme_unmap_metadata(dev, req); + nvme_unmap_metadata(dev, nvmeq, req); if (blk_rq_nr_phys_segments(req)) - nvme_unmap_data(dev, req); + nvme_unmap_data(dev, nvmeq, req); } static void nvme_pci_complete_rq(struct request *req) { nvme_pci_unmap_rq(req); @@ -2839,39 +2897,10 @@ static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) return -EBUSY; nvme_dev_disable(dev, shutdown); return 0; } -static int nvme_setup_prp_pools(struct nvme_dev *dev) -{ - size_t small_align = 256; - - dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, - NVME_CTRL_PAGE_SIZE, - NVME_CTRL_PAGE_SIZE, 0); - if (!dev->prp_page_pool) - return -ENOMEM; - - if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512) - small_align = 512; - - /* Optimisation for I/Os between 4k and 128k */ - dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, - 256, small_align, 0); - if (!dev->prp_small_pool) { - dma_pool_destroy(dev->prp_page_pool); - return -ENOMEM; - } - return 0; -} - -static void nvme_release_prp_pools(struct nvme_dev *dev) -{ - dma_pool_destroy(dev->prp_page_pool); - dma_pool_destroy(dev->prp_small_pool); -} - static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) { size_t meta_size = sizeof(struct scatterlist) * (NVME_MAX_META_SEGS + 1); size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS; @@ -3182,11 +3211,12 @@ static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, unsigned long quirks = id->driver_data; int node = dev_to_node(&pdev->dev); struct nvme_dev *dev; int ret = -ENOMEM; - dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); + dev = kzalloc_node(sizeof(*dev) + nr_node_ids * sizeof(*dev->prp_pools), + GFP_KERNEL, node); if (!dev) return ERR_PTR(-ENOMEM); INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); mutex_init(&dev->shutdown_lock); @@ -3257,17 +3287,13 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) result = nvme_dev_map(dev); if (result) goto out_uninit_ctrl; - result = nvme_setup_prp_pools(dev); - if (result) - goto out_dev_unmap; - result = nvme_pci_alloc_iod_mempool(dev); if (result) - goto out_release_prp_pools; + goto out_dev_unmap; dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); result = nvme_pci_enable(dev); if (result) @@ -3339,12 +3365,10 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) nvme_dbbuf_dma_free(dev); nvme_free_queues(dev, 0); out_release_iod_mempool: mempool_destroy(dev->iod_mempool); mempool_destroy(dev->iod_meta_mempool); -out_release_prp_pools: - nvme_release_prp_pools(dev); out_dev_unmap: nvme_dev_unmap(dev); out_uninit_ctrl: nvme_uninit_ctrl(&dev->ctrl); out_put_ctrl: -- 2.45.2