From: Borislav Petkov <bp@alien8.de>
To: shiju.jose@huawei.com
Cc: linux-cxl@vger.kernel.org, dan.j.williams@intel.com,
dave@stgolabs.net, jonathan.cameron@huawei.com,
dave.jiang@intel.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com, david@redhat.com,
Vilas.Sridharan@amd.com, linux-edac@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-mm@kvack.org,
linux-kernel@vger.kernel.org, tony.luck@intel.com,
rafael@kernel.org, lenb@kernel.org, mchehab@kernel.org,
leo.duran@amd.com, Yazen.Ghannam@amd.com, rientjes@google.com,
jiaqiyan@google.com, Jon.Grimm@amd.com,
dave.hansen@linux.intel.com, naoya.horiguchi@nec.com,
james.morse@arm.com, jthoughton@google.com,
somasundaram.a@hpe.com, erdemaktas@google.com, pgonda@google.com,
duenwen@google.com, gthelen@google.com,
wschwartz@amperecomputing.com, dferguson@amperecomputing.com,
wbs@os.amperecomputing.com, nifan.cxl@gmail.com,
tanxiaofei@huawei.com, prime.zeng@hisilicon.com,
roberto.sassu@huawei.com, kangkang.shen@futurewei.com,
wanghuiqiang@huawei.com, linuxarm@huawei.com
Subject: Re: [PATCH v2 7/8] cxl/memfeature: Add CXL memory device soft PPR control feature
Date: Thu, 27 Mar 2025 18:01:56 +0100 [thread overview]
Message-ID: <20250327170156.GCZ-WEhNREaxQaH_ya@fat_crate.local> (raw)
In-Reply-To: <20250320180450.539-8-shiju.jose@huawei.com>
On Thu, Mar 20, 2025 at 06:04:44PM +0000, shiju.jose@huawei.com wrote:
> diff --git a/drivers/edac/mem_repair.c b/drivers/edac/mem_repair.c
> index 3b1a845457b0..bf7e01a8b4dd 100755
> --- a/drivers/edac/mem_repair.c
> +++ b/drivers/edac/mem_repair.c
> @@ -45,6 +45,11 @@ struct edac_mem_repair_context {
> struct attribute_group group;
> };
>
> +const char * const edac_repair_type[] = {
> + [EDAC_PPR] = "ppr",
> +};
> +EXPORT_SYMBOL_GPL(edac_repair_type);
Why is this thing exported instead of adding a getter function and having all
its users pass in proper defines as arguments?
And "EDAC_PPR" is not a proper define - it doesn't tell me what it is.
It should be more likely a
EDAC_REPAIR_PPR,
EDAC_REPAIR_ROW_SPARING,
EDAC_REPAIR_BANK_SPARING,
and so on.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2025-03-27 17:02 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 18:04 [PATCH v2 0/8] cxl: support CXL memory RAS features shiju.jose
2025-03-20 18:04 ` [PATCH v2 1/8] cxl: Add helper function to retrieve a feature entry shiju.jose
2025-03-26 21:32 ` Dan Williams
2025-03-27 16:59 ` Shiju Jose
2025-03-31 23:35 ` Dan Williams
2025-03-20 18:04 ` [PATCH v2 2/8] EDAC: Update documentation for the CXL memory patrol scrub control feature shiju.jose
2025-03-21 10:03 ` Jonathan Cameron
2025-03-24 10:37 ` Shiju Jose
2025-03-26 21:46 ` Dan Williams
2025-03-20 18:04 ` [PATCH v2 3/8] cxl/edac: Add CXL memory device " shiju.jose
2025-03-27 1:47 ` Dan Williams
2025-03-28 10:18 ` Shiju Jose
2025-03-20 18:04 ` [PATCH v2 4/8] cxl/edac: Add CXL memory device ECS " shiju.jose
2025-03-27 17:12 ` Dan Williams
2025-03-20 18:04 ` [PATCH v2 5/8] cxl/mbox: Add support for PERFORM_MAINTENANCE mailbox command shiju.jose
2025-03-27 17:23 ` Dan Williams
2025-03-20 18:04 ` [PATCH v2 6/8] cxl: Support for finding memory operation attributes from the current boot shiju.jose
2025-03-27 17:43 ` Dan Williams
2025-03-20 18:04 ` [PATCH v2 7/8] cxl/memfeature: Add CXL memory device soft PPR control feature shiju.jose
2025-03-27 17:01 ` Borislav Petkov [this message]
2025-03-27 17:08 ` Borislav Petkov
2025-03-28 13:05 ` Shiju Jose
2025-03-20 18:04 ` [PATCH v2 8/8] cxl/memfeature: Add CXL memory device memory sparing " shiju.jose
2025-03-21 7:39 ` [PATCH v2 0/8] cxl: support CXL memory RAS features Christophe Leroy
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