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Fri, 7 Mar 2025 02:01:48 +0100 Date: Fri, 7 Mar 2025 09:01:43 +0800 From: Jonathan Cameron To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH 3/8] cxl/memfeature: Add CXL memory device ECS control feature Message-ID: <20250307090143.00003e3f@huawei.com> In-Reply-To: <20250227223816.2036-4-shiju.jose@huawei.com> References: <20250227223816.2036-1-shiju.jose@huawei.com> <20250227223816.2036-4-shiju.jose@huawei.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.43.65] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To frapeml500008.china.huawei.com (7.182.85.71) X-Rspamd-Server: rspam08 X-Rspamd-Queue-Id: F06B1A0013 X-Stat-Signature: iuybonjapwfefxw9chnuko87ccsugyw5 X-Rspam-User: X-HE-Tag: 1741309323-145238 X-HE-Meta: U2FsdGVkX19yRVUerWyzWVvEkVIO/gPevGWvVuGOihur3JwX8qdHSEn1xxfH6KUK8DN7Zyp4mWerDe+/UHFMFeB7BUMP1vAudMBx+EmhkmFlEZPjzmGczJDDzOXoNjySA0hJxyKp5ru1F1RNKK+p9fWfAcr3H9P/nb8HwfmZntk+PQoRX/4fGP6UMGeMGI4nKA1rQomcy/hn6zZ91qaC9Hq8+aytZrg2o3mGstCu4cnZs5OT10lJTb5lxqpfRRf4S8zsDliX7tL2q6Lb0iV05xGJVM8uIeiFPtNwGb5pQAfXfAJoyrQPl8EuuWDmsNnHWb6fmd8QVZFINVQhiODzuVe91AA3f2oGJQUVwgIyxuTl4roonY2bs0TPn+LHvGfoNuqpC11s2YJ7AiiXODaHbXMivXJbyA+XF9qo2HflTDdHliUOfbr5ItXTqBUzEYaVYH4j+qMHNFbQT/4hp8r7I3zSwwuiWst0KTQeKcGukB6POI+5lyA/+XG6bt1CEQS0McTuM9mg2OLtDb5ZlW0iSM8OovkpNk7cz7jD/EiPE7D2aHDAIL+t4jrfZmrbNHnt5osfWctiuA4G5la4QQ3GMs/GwkIxMpzISma6hAf3d75QF9tnYHeZk7D0BjoTD4o1u1Eye0R7VKSj5HUHmmWF8XnQ+yPUIDz3YfGgXAvgEHER7t9TV47HXOO81KrgDZF2jJku1024Nt3pwKoBlke3jGa3lsptd6KUc2f2MLyOxxFIcZhIYB1MEync+R7vxStrYCDUXkIqdUq51124cgAHe34NEhGnmSxrnPhZsLWciSqzkI0F7E6yX9vQTkQE5qG3fmnvwADj2EgBUfo95pb9g2XGsvMd+jG0fnAQFQOndcu2HkWJxjbBrOIwgTYRXIOU/oYNu6amLpZq1Dvdgas5Zk98+IeKTvani8MKc0Rp8f7+ZaniOS2arhKplUpaATm92CzaW6UeTNcpOOxVMgf t7KJdn7F VJHXXqKIHN0FAmH86uhM0ScRm0Dx6VusYYAMRDx/jEHux07FWc/tbjE+C7MXnUWetd8C+MzmPu3HSHK7mVwoICoSPjRU0Guh0vEks/+7kSl5r93GNhaeQTB7SliMBTaVu3ooFi3RtIzqDvvB2t/4SLVU1stUA3yz/f6vRvBtT5oxUslGCSQEkOwDp2BHAOQsV3AVpO7st7VczEAkuo11ipZjuyJyU/kr69Ee4GNFbAhxe+vjjv4tkYN43iGGb25i0fLTNxFgu9/krIqDMy+XP7vw/Hj9Sy1nr5nTsLJAs+pkVxjpnDynWqT4YRw== X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: On Thu, 27 Feb 2025 22:38:10 +0000 wrote: > From: Shiju Jose > > CXL spec 3.2 section 8.2.10.9.11.2 describes the DDR5 ECS (Error Check > Scrub) control feature. > The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM > Specification (JESD79-5) and allows the DRAM to internally read, correct > single-bit errors, and write back corrected data bits to the DRAM array > while providing transparency to error counts. > > The ECS control allows the requester to change the log entry type, the ECS > threshold count (provided the request falls within the limits specified in > DDR5 mode registers), switch between codeword mode and row count mode, and > reset the ECS counter. > > Register with EDAC device driver, which retrieves the ECS attribute > descriptors from the EDAC ECS and exposes the ECS control attributes to > userspace via sysfs. For example, the ECS control for the memory media FRU0 > in CXL mem0 device is located at /sys/bus/edac/devices/cxl_mem0/ecs_fru0/ > > Signed-off-by: Shiju Jose Hmm. No idea why I didn't tag this before. It's been fine for ages. One really small thing if respinning for some other reason, Reviewed-by: Jonathan Cameron > +static int cxl_mem_ecs_set_attrs(struct device *dev, > + struct cxl_ecs_context *cxl_ecs_ctx, > + int fru_id, struct cxl_ecs_params *params, > + u8 param_type) > +{ ... > + > + /* > + * Fill attribute to be set for the media FRU Trivial but could be a single line comment. > + */ > + ecs_config = le16_to_cpu(fru_rd_attrs[fru_id].ecs_config); > + switch (param_type) { > + case CXL_ECS_PARAM_LOG_ENTRY_TYPE: