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From: Borislav Petkov <bp@alien8.de>
To: Manali.Shukla@amd.com, thomas.lendacky@amd.com
Cc: Borislav Petkov <bp@kernel.org>,
	riel@surriel.com, akpm@linux-foundation.org,
	andrew.cooper3@citrix.com, jackmanb@google.com, jannh@google.com,
	kernel-team@meta.com, linux-kernel@vger.kernel.org,
	linux-mm@kvack.org, mhklinux@outlook.com, nadav.amit@gmail.com,
	x86@kernel.org, zhengqi.arch@bytedance.com
Subject: Re: [PATCH v15 02/11] x86/mm: Add INVLPGB feature and Kconfig entry
Date: Wed, 5 Mar 2025 13:01:41 +0100	[thread overview]
Message-ID: <20250305120141.GGZ8g9JU-IaaNNgTRb@fat_crate.local> (raw)
In-Reply-To: <20250304135816.12356-3-bp@kernel.org>

On Tue, Mar 04, 2025 at 02:58:07PM +0100, Borislav Petkov wrote:
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 508c0dad116b..8770dc185fe9 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -338,6 +338,7 @@
>  #define X86_FEATURE_CLZERO		(13*32+ 0) /* "clzero" CLZERO instruction */
>  #define X86_FEATURE_IRPERF		(13*32+ 1) /* "irperf" Instructions Retired Count */
>  #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
> +#define X86_FEATURE_INVLPGB		(13*32+ 3) /* INVLPGB and TLBSYNC instructions supported */
>  #define X86_FEATURE_RDPRU		(13*32+ 4) /* "rdpru" Read processor register at user level */
>  #define X86_FEATURE_WBNOINVD		(13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
>  #define X86_FEATURE_AMD_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */
> diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h
> index c492bdc97b05..625a89259968 100644
> --- a/arch/x86/include/asm/disabled-features.h
> +++ b/arch/x86/include/asm/disabled-features.h
> @@ -129,6 +129,12 @@
>  #define DISABLE_SEV_SNP		(1 << (X86_FEATURE_SEV_SNP & 31))
>  #endif
>  
> +#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH

Manali caught this: I forgot this one place yesterday when converting because
of the tip patch zapping and branch rebasing tetris...

With that fixed, Tom's patch with the guest ASID valid bit set works too:

https://lore.kernel.org/r/20250304120449.GHZ8bsYYyEBOKQIxBm@fat_crate.local

I'll push a new branch soon.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette


  reply	other threads:[~2025-03-05 19:08 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-04 13:58 [PATCH v15 00/11] AMD broadcast TLB invalidation Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 01/11] x86/mm: Consolidate full flush threshold decision Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 02/11] x86/mm: Add INVLPGB feature and Kconfig entry Borislav Petkov
2025-03-05 12:01   ` Borislav Petkov [this message]
2025-03-04 13:58 ` [PATCH v15 03/11] x86/mm: Add INVLPGB support code Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 04/11] x86/mm: Use INVLPGB for kernel TLB flushes Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 05/11] x86/mm: Use broadcast TLB flushing in page reclaim Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 06/11] x86/mm: Add global ASID allocation helper functions Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 07/11] x86/mm: Handle global ASID context switch and TLB flush Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 08/11] x86/mm: Add global ASID process exit helpers Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 09/11] x86/mm: Enable broadcast TLB invalidation for multi-threaded processes Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 10/11] x86/mm: Do targeted broadcast flushing from tlbbatch code Borislav Petkov
2025-03-04 13:58 ` [PATCH v15 11/11] x86/mm: Enable AMD translation cache extensions Borislav Petkov

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