From: Peter Zijlstra <peterz@infradead.org>
To: Rik van Riel <riel@surriel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de,
dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com,
nadav.amit@gmail.com, thomas.lendacky@amd.com,
kernel-team@meta.com, linux-mm@kvack.org,
akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com,
mhklinux@outlook.com, andrew.cooper3@citrix.com,
Manali Shukla <Manali.Shukla@amd.com>
Subject: Re: [PATCH v10 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes
Date: Wed, 12 Feb 2025 11:22:42 +0100 [thread overview]
Message-ID: <20250212102242.GB24784@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20250212095438.GC19118@noisy.programming.kicks-ass.net>
On Wed, Feb 12, 2025 at 10:54:38AM +0100, Peter Zijlstra wrote:
> On Tue, Feb 11, 2025 at 04:08:04PM -0500, Rik van Riel wrote:
>
> > +static void broadcast_tlb_flush(struct flush_tlb_info *info)
> > +{
> > + bool pmd = info->stride_shift == PMD_SHIFT;
> > + unsigned long maxnr = invlpgb_count_max;
> > + unsigned long asid = info->mm->context.global_asid;
> > + unsigned long addr = info->start;
> > + unsigned long nr;
> > +
> > + /* Flushing multiple pages at once is not supported with 1GB pages. */
> > + if (info->stride_shift > PMD_SHIFT)
> > + maxnr = 1;
>
> How does this work?
>
> Normally, if we get a 1GB range, we'll iterate on the stride and INVLPG
> each one (just like any other stride).
>
> Should you not instead either force the stride down to PMD level or
> force a full flush?
Oh, n/m, I think I see.
next prev parent reply other threads:[~2025-02-12 10:23 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-11 21:07 [PATCH v10 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-02-11 21:07 ` [PATCH v10 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-02-11 21:07 ` [PATCH v10 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-02-11 21:07 ` [PATCH v10 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-02-11 21:07 ` [PATCH v10 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-11 21:08 ` [PATCH v10 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-02-11 21:08 ` [PATCH v10 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-11 21:08 ` [PATCH v10 07/12] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-11 21:08 ` [PATCH v10 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-11 21:08 ` [PATCH v10 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-02-12 9:54 ` Peter Zijlstra
2025-02-12 10:22 ` Peter Zijlstra [this message]
2025-02-12 10:42 ` Peter Zijlstra
2025-02-12 12:07 ` Nadav Amit
2025-02-12 13:28 ` Brendan Jackman
2025-02-11 21:08 ` [PATCH v10 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-02-12 13:32 ` Brendan Jackman
2025-02-11 21:08 ` [PATCH v10 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-02-11 21:08 ` [PATCH v10 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-02-12 10:23 ` [PATCH v10 00/12] AMD broadcast TLB invalidation Peter Zijlstra
2025-02-12 10:44 ` Brendan Jackman
2025-02-12 10:59 ` Peter Zijlstra
2025-02-12 15:39 ` Rik van Riel
2025-02-13 13:03 ` Borislav Petkov
2025-02-12 16:30 ` Sean Christopherson
2025-02-12 20:35 ` Michael Kelley
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