From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80DBFC0219D for ; Tue, 11 Feb 2025 21:09:29 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 5751F280006; Tue, 11 Feb 2025 16:09:10 -0500 (EST) Received: by kanga.kvack.org (Postfix, from userid 40) id 4FCA8280004; Tue, 11 Feb 2025 16:09:10 -0500 (EST) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 2E734280006; Tue, 11 Feb 2025 16:09:10 -0500 (EST) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0015.hostedemail.com [216.40.44.15]) by kanga.kvack.org (Postfix) with ESMTP id 02EB0280004 for ; Tue, 11 Feb 2025 16:09:09 -0500 (EST) Received: from smtpin26.hostedemail.com (a10.router.float.18 [10.200.18.1]) by unirelay06.hostedemail.com (Postfix) with ESMTP id B5CB9B137C for ; Tue, 11 Feb 2025 21:09:09 +0000 (UTC) X-FDA: 83108904018.26.1538276 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) by imf10.hostedemail.com (Postfix) with ESMTP id 3600DC0013 for ; Tue, 11 Feb 2025 21:09:08 +0000 (UTC) Authentication-Results: imf10.hostedemail.com; dkim=none; spf=pass (imf10.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=hostedemail.com; s=arc-20220608; t=1739308148; h=from:from:sender:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5jyuLSMzlUYDWRskKJb6Xc0QSC8f69gZO1sgMf59NT0=; b=f91Bklavo9O1S/7c9JZ/490iNKOVEShZpSFbP+7v9+5VWfTC544ANGBVZqLlHFehmwXUj7 DDpWQyaPE/dmfkFsxtRu8gpfS3nYLphC8B6m1v+ksjeTHCbj84D0r+N9aTsAarfe2f2XuV C8fzeA+JQ0T/MiaxI7+U7omn8f5bXmI= ARC-Authentication-Results: i=1; imf10.hostedemail.com; dkim=none; spf=pass (imf10.hostedemail.com: domain of riel@shelob.surriel.com designates 96.67.55.147 as permitted sender) smtp.mailfrom=riel@shelob.surriel.com; dmarc=none ARC-Seal: i=1; s=arc-20220608; d=hostedemail.com; t=1739308148; a=rsa-sha256; cv=none; b=xHIJYPWeQwz0IfivfW/KJSUYHBbQIMmW7eCOVZaRDsTvXaxVQDS/8WTdCU2IoqMh+shBVa 2F5ZaQdLCOx0hzn8HzqMHmcjawqtiH9y9Oh6LpLoLtuDtfCp95vFd/BxaG0KNeVMJ5abQt tFNTCR0916ISIyXAe+qhEbdfxc1YTqo= Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1thxUX-000000008HU-3Re4; Tue, 11 Feb 2025 16:08:25 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jackmanb@google.com, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Manali Shukla Subject: [PATCH v10 11/12] x86/mm: enable AMD translation cache extensions Date: Tue, 11 Feb 2025 16:08:06 -0500 Message-ID: <20250211210823.242681-12-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250211210823.242681-1-riel@surriel.com> References: <20250211210823.242681-1-riel@surriel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Rspam-User: X-Rspamd-Server: rspam11 X-Rspamd-Queue-Id: 3600DC0013 X-Stat-Signature: k8wihdqopebgwp9ettnrn6at7o7czpg9 X-HE-Tag: 1739308148-849864 X-HE-Meta: U2FsdGVkX18+PcaWUgCa1ddWRwsMSdY+luQ9WYHuLVdzvJqyxdzPOUZOI5nYCu0nZdUyeYsO6UsejOzsDa4vW0nAggEOr53CRvReMEuDklxUXFcORqhp3NVIP0fj+fT1OENnUTpCJNxoIwA5HBFGoFyEaTV7jjZNI1CXTs9mTVyeWlHJEgLl/WNuiTLImoRtZLCjOHUBjqUqSGmjFELazOM6EihV0dWYkZXUj1LAoOFLcEZpw0exBWac3C4rYqrvmCths+zmY2PML68ZcW9oBmOhdWtRBDGeKhQgLLdPK/FudUb/8p5avmNQQTYnPkR8kCX4fMs7kVqT0JW17XAUAGjVgVAtf7TGOCtoJff+TwkRrP5FVCK6z0Q/Bl6Vhz9A1cHnpVibQbfbgIKd7yqaAJhKuasgo5TgNQKO92JY/bnxVx0fyrT+9rGLRC1oMiD7kFS2LP65H+rWKpdXC9x7D9tboXQLIZ2nEhQFmt8oPUF6viYyc3vHpWoLKw5WS8szRTdn2+X4K+fHn5pcu550e/wHuPIOidrvg5cBl9NfzHn633tJqFQAJtAAqSRiViV9OdWWxfxfY8NUhajnupdACvYTaak7npaMVxq8F64Waj8wb7jSXeSsQTH67AbAQqh3/0fWGQWnQyx8iWSKniGaylUd9nI0lZipgxXSlqrLWoWohwWkH6jn/bQs40r1+xg0YsariwkbunPplKLdmlz5naNN+l9HZlwLJDlKSEKlzLvLl6ukcj2Vn9wyWesziGOGHy3sXFbyIRqjyrQ6sKDoi2XP8g+jYcfyRI42Wkx3s/28ie3h8RsrpWbCbZH50XxxfdI7LhaF6ha5KpXBXz/+GsE9gwPTkecf6etPlycanwWmt65LYjiJLKP91DcDx1yUPNtw0q58u+9AhfGGzMRJ1zK1yJQwl1bKZPyVBEUybLATZjHIfTPZqT70HLBR2NF3Xi6MZg2AdSzSvauALkY RPlQR2EN yDfVQjYfB+Z3oWxfiJCSk9vwxInKYETjypZpQsXZH2aXnIq+M6RRoMNKgh308d0yQ9xp0coMt9E2B8glgWMqDv0NSPUUH40E5Q5YxM1cIJAzXebvs7uQ1156cspLH1OnTQnIXJDr+wOHpdzYjE+nc7ZmEl3Eo/1AzRoybNlzL2eOufrkSKVQHVx/VoOJkQibtpbQ36KtVT//BWxcMK6oWTsVOVL+7tBXi32WQIhH2mfa7l33MHte2AqZqVmGHGlKLT9nXhpuVEDoz0E/ZD2Jn8Dpe3UXarUwq/xjUoxW78VtXsJ420/XUYy5QJgI0gusjxJ66y+ynXXW5ajxne014rHfrYF47tPcO2q6XQdbR9FE7wgPBORyIJgqyJUupGCgsV1x/uWFNr1urMFBeNvBR1kWfs/vMi4X5eAqLaCn5+xuB9kYQUpJWY+96+xX3T7Rs2/DyZIe1fYfQurFaK5tKEf2Ge1VJAwWU16Xh8Z1p4JaaaTSuLj9xGro8GIrCroIVWNq/b/mDYoMxtZE= X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: List-Subscribe: List-Unsubscribe: With AMD TCE (translation cache extensions) only the intermediate mappings that cover the address range zapped by INVLPG / INVLPGB get invalidated, rather than all intermediate mappings getting zapped at every TLB invalidation. This can help reduce the TLB miss rate, by keeping more intermediate mappings in the cache. >From the AMD manual: Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on TLB entries. When this bit is 0, these instructions remove the target PTE from the TLB as well as all upper-level table entries that are cached in the TLB, whether or not they are associated with the target PTE. When this bit is set, these instructions will remove the target PTE and only those upper-level entries that lead to the target PTE in the page table hierarchy, leaving unrelated upper-level entries intact. Signed-off-by: Rik van Riel Tested-by: Manali Shukla Tested-by: Brendan Jackman --- arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/kernel/cpu/amd.c | 4 ++++ tools/arch/x86/include/asm/msr-index.h | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..dc1c1057f26e 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index bcf73775b4f8..21076252a491 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1071,6 +1071,10 @@ static void init_amd(struct cpuinfo_x86 *c) /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */ clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); + + /* Enable Translation Cache Extension */ + if (cpu_feature_enabled(X86_FEATURE_TCE)) + msr_set_bit(MSR_EFER, _EFER_TCE); } #ifdef CONFIG_X86_32 diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 3ae84c3b8e6d..dc1c1057f26e 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -25,6 +25,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_TCE 15 /* Enable Translation Cache Extensions */ #define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */ #define EFER_SCE (1<<_EFER_SCE) @@ -34,6 +35,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_TCE (1<<_EFER_TCE) #define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* -- 2.47.1