From: Deepak Gupta <debug@rivosinc.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Andrew Morton <akpm@linux-foundation.org>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
Vlastimil Babka <vbabka@suse.cz>,
Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Christian Brauner <brauner@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Oleg Nesterov <oleg@redhat.com>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <kees@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <shuah@kernel.org>, Jann Horn <jannh@google.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
alistair.francis@wdc.com, richard.henderson@linaro.org,
jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com,
charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com,
cleger@rivosinc.com, alexghiti@rivosinc.com,
samitolvanen@google.com, broonie@kernel.org,
rick.p.edgecombe@intel.com, Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v10 23/27] arch/riscv: compile vdso with landing pad
Date: Mon, 10 Feb 2025 12:26:56 -0800 [thread overview]
Message-ID: <20250210-v5_user_cfi_series-v10-23-163dcfa31c60@rivosinc.com> (raw)
In-Reply-To: <20250210-v5_user_cfi_series-v10-0-163dcfa31c60@rivosinc.com>
From: Jim Shu <jim.shu@sifive.com>
user mode tasks compiled with zicfilp may call indirectly into vdso (like
hwprobe indirect calls). Add landing pad compile support in vdso. vdso
with landing pad in it will be nop for tasks which have not enabled
landing pad.
This patch allows to run user mode tasks with cfi eanbled and do no harm.
Future work can be done on this to do below
- labeled landing pad on vdso functions (whenever labeling support shows
up in gnu-toolchain)
- emit shadow stack instructions only in vdso compiled objects as part of
kernel compile.
Signed-off-by: Jim Shu <jim.shu@sifive.com>
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
arch/riscv/Makefile | 7 +++++-
arch/riscv/include/asm/assembler.h | 44 +++++++++++++++++++++++++++++++++++
arch/riscv/kernel/vdso/Makefile | 8 +++++++
arch/riscv/kernel/vdso/flush_icache.S | 4 ++++
arch/riscv/kernel/vdso/getcpu.S | 4 ++++
arch/riscv/kernel/vdso/rt_sigreturn.S | 4 ++++
arch/riscv/kernel/vdso/sys_hwprobe.S | 4 ++++
7 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 13fbc0f94238..ea9468af2cb4 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -87,10 +87,15 @@ riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZACAS) := $(riscv-march-y)_zacas
# Check if the toolchain supports Zabha
riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZABHA) := $(riscv-march-y)_zabha
+# Check if the toolchain supports Zihintpause extension
+riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
+
+KBUILD_BASE_ISA = -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
+export KBUILD_BASE_ISA
# Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by
# matching non-v and non-multi-letter extensions out with the filter ([^v_]*)
-KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\2/')
+KBUILD_CFLAGS += $(KBUILD_BASE_ISA)
KBUILD_AFLAGS += -march=$(riscv-march-y)
diff --git a/arch/riscv/include/asm/assembler.h b/arch/riscv/include/asm/assembler.h
index 44b1457d3e95..edbe86d0b4f7 100644
--- a/arch/riscv/include/asm/assembler.h
+++ b/arch/riscv/include/asm/assembler.h
@@ -80,3 +80,47 @@
.endm
#endif /* __ASM_ASSEMBLER_H */
+
+#if defined(CONFIG_RISCV_USER_CFI) && (__riscv_xlen == 64)
+.macro vdso_lpad
+lpad 1
+.endm
+#else
+.macro vdso_lpad
+.endm
+#endif
+
+/*
+ * This macro emits a program property note section identifying
+ * architecture features which require special handling, mainly for
+ * use in assembly files included in the VDSO.
+ */
+#define NT_GNU_PROPERTY_TYPE_0 5
+#define GNU_PROPERTY_RISCV_FEATURE_1_AND 0xc0000000
+
+#define GNU_PROPERTY_RISCV_FEATURE_1_ZICFILP (1U << 0)
+#define GNU_PROPERTY_RISCV_FEATURE_1_ZICFISS (1U << 1)
+
+#if defined(CONFIG_RISCV_USER_CFI) && (__riscv_xlen == 64)
+#define GNU_PROPERTY_RISCV_FEATURE_1_DEFAULT \
+ (GNU_PROPERTY_RISCV_FEATURE_1_ZICFILP)
+#endif
+
+#ifdef GNU_PROPERTY_RISCV_FEATURE_1_DEFAULT
+.macro emit_riscv_feature_1_and, feat = GNU_PROPERTY_RISCV_FEATURE_1_DEFAULT
+ .pushsection .note.gnu.property, "a"
+ .p2align 3
+ .word 4
+ .word 16
+ .word NT_GNU_PROPERTY_TYPE_0
+ .asciz "GNU"
+ .word GNU_PROPERTY_RISCV_FEATURE_1_AND
+ .word 4
+ .word \feat
+ .word 0
+ .popsection
+.endm
+#else
+.macro emit_riscv_feature_1_and, feat = 0
+.endm
+#endif
diff --git a/arch/riscv/kernel/vdso/Makefile b/arch/riscv/kernel/vdso/Makefile
index 9a1b555e8733..93c134f0afb1 100644
--- a/arch/riscv/kernel/vdso/Makefile
+++ b/arch/riscv/kernel/vdso/Makefile
@@ -19,6 +19,8 @@ obj-vdso = $(patsubst %, %.o, $(vdso-syms)) note.o
ccflags-y := -fno-stack-protector
ccflags-y += -DDISABLE_BRANCH_PROFILING
ccflags-y += -fno-builtin
+ccflags-y += $(KBUILD_BASE_ISA)_zicfilp
+asflags-y += $(KBUILD_BASE_ISA)_zicfilp
ifneq ($(c-gettimeofday-y),)
CFLAGS_vgettimeofday.o += -fPIC -include $(c-gettimeofday-y)
@@ -40,6 +42,12 @@ endif
CFLAGS_REMOVE_vgettimeofday.o = $(CC_FLAGS_FTRACE) $(CC_FLAGS_SCS)
CFLAGS_REMOVE_hwprobe.o = $(CC_FLAGS_FTRACE) $(CC_FLAGS_SCS)
+# Disable profiling and instrumentation for VDSO code
+GCOV_PROFILE := n
+KCOV_INSTRUMENT := n
+KASAN_SANITIZE := n
+UBSAN_SANITIZE := n
+
# Force dependency
$(obj)/vdso.o: $(obj)/vdso.so
diff --git a/arch/riscv/kernel/vdso/flush_icache.S b/arch/riscv/kernel/vdso/flush_icache.S
index 8f884227e8bc..e4c56970905e 100644
--- a/arch/riscv/kernel/vdso/flush_icache.S
+++ b/arch/riscv/kernel/vdso/flush_icache.S
@@ -5,11 +5,13 @@
#include <linux/linkage.h>
#include <asm/unistd.h>
+#include <asm/assembler.h>
.text
/* int __vdso_flush_icache(void *start, void *end, unsigned long flags); */
SYM_FUNC_START(__vdso_flush_icache)
.cfi_startproc
+ vdso_lpad
#ifdef CONFIG_SMP
li a7, __NR_riscv_flush_icache
ecall
@@ -20,3 +22,5 @@ SYM_FUNC_START(__vdso_flush_icache)
ret
.cfi_endproc
SYM_FUNC_END(__vdso_flush_icache)
+
+emit_riscv_feature_1_and
diff --git a/arch/riscv/kernel/vdso/getcpu.S b/arch/riscv/kernel/vdso/getcpu.S
index 9c1bd531907f..5c1ecc4e1465 100644
--- a/arch/riscv/kernel/vdso/getcpu.S
+++ b/arch/riscv/kernel/vdso/getcpu.S
@@ -5,14 +5,18 @@
#include <linux/linkage.h>
#include <asm/unistd.h>
+#include <asm/assembler.h>
.text
/* int __vdso_getcpu(unsigned *cpu, unsigned *node, void *unused); */
SYM_FUNC_START(__vdso_getcpu)
.cfi_startproc
+ vdso_lpad
/* For now, just do the syscall. */
li a7, __NR_getcpu
ecall
ret
.cfi_endproc
SYM_FUNC_END(__vdso_getcpu)
+
+emit_riscv_feature_1_and
diff --git a/arch/riscv/kernel/vdso/rt_sigreturn.S b/arch/riscv/kernel/vdso/rt_sigreturn.S
index 3dc022aa8931..e82987dc3739 100644
--- a/arch/riscv/kernel/vdso/rt_sigreturn.S
+++ b/arch/riscv/kernel/vdso/rt_sigreturn.S
@@ -5,12 +5,16 @@
#include <linux/linkage.h>
#include <asm/unistd.h>
+#include <asm/assembler.h>
.text
SYM_FUNC_START(__vdso_rt_sigreturn)
.cfi_startproc
.cfi_signal_frame
+ vdso_lpad
li a7, __NR_rt_sigreturn
ecall
.cfi_endproc
SYM_FUNC_END(__vdso_rt_sigreturn)
+
+emit_riscv_feature_1_and
diff --git a/arch/riscv/kernel/vdso/sys_hwprobe.S b/arch/riscv/kernel/vdso/sys_hwprobe.S
index 77e57f830521..f1694451a60c 100644
--- a/arch/riscv/kernel/vdso/sys_hwprobe.S
+++ b/arch/riscv/kernel/vdso/sys_hwprobe.S
@@ -3,13 +3,17 @@
#include <linux/linkage.h>
#include <asm/unistd.h>
+#include <asm/assembler.h>
.text
SYM_FUNC_START(riscv_hwprobe)
.cfi_startproc
+ vdso_lpad
li a7, __NR_riscv_hwprobe
ecall
ret
.cfi_endproc
SYM_FUNC_END(riscv_hwprobe)
+
+emit_riscv_feature_1_and
--
2.34.1
next prev parent reply other threads:[~2025-02-10 20:27 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 20:26 [PATCH v10 00/27] riscv control-flow integrity for usermode Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 01/27] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 03/27] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 07/27] riscv mm: manufacture shadow stack pte Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 08/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 09/27] riscv mmu: write protect and shadow stack Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 10/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 11/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 12/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 13/27] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 14/27] riscv/traps: Introduce software check exception Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 15/27] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 16/27] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 17/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 18/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 19/27] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 20/27] riscv: Add Firmware Feature SBI extensions definitions Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 21/27] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 22/27] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-02-10 20:26 ` Deepak Gupta [this message]
2025-02-10 20:26 ` [PATCH v10 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-02-10 20:27 ` [PATCH v10 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
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