From: Deepak Gupta <debug@rivosinc.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
Andrew Morton <akpm@linux-foundation.org>,
"Liam R. Howlett" <Liam.Howlett@oracle.com>,
Vlastimil Babka <vbabka@suse.cz>,
Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Christian Brauner <brauner@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Oleg Nesterov <oleg@redhat.com>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <kees@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <shuah@kernel.org>, Jann Horn <jannh@google.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
linux-mm@kvack.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
alistair.francis@wdc.com, richard.henderson@linaro.org,
jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com,
charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com,
cleger@rivosinc.com, alexghiti@rivosinc.com,
samitolvanen@google.com, broonie@kernel.org,
rick.p.edgecombe@intel.com, Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v10 14/27] riscv/traps: Introduce software check exception
Date: Mon, 10 Feb 2025 12:26:47 -0800 [thread overview]
Message-ID: <20250210-v5_user_cfi_series-v10-14-163dcfa31c60@rivosinc.com> (raw)
In-Reply-To: <20250210-v5_user_cfi_series-v10-0-163dcfa31c60@rivosinc.com>
zicfiss / zicfilp introduces a new exception to priv isa `software check
exception` with cause code = 18. This patch implements software check
exception.
Additionally it implements a cfi violation handler which checks for code
in xtval. If xtval=2, it means that sw check exception happened because of
an indirect branch not landing on 4 byte aligned PC or not landing on
`lpad` instruction or label value embedded in `lpad` not matching label
value setup in `x7`. If xtval=3, it means that sw check exception happened
because of mismatch between link register (x1 or x5) and top of shadow
stack (on execution of `sspopchk`).
In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR.
SEGV_CPERR was introduced by x86 shadow stack patches.
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
arch/riscv/include/asm/asm-prototypes.h | 1 +
arch/riscv/include/asm/entry-common.h | 2 ++
arch/riscv/kernel/entry.S | 3 +++
arch/riscv/kernel/traps.c | 43 +++++++++++++++++++++++++++++++++
4 files changed, 49 insertions(+)
diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h
index cd627ec289f1..5a27cefd7805 100644
--- a/arch/riscv/include/asm/asm-prototypes.h
+++ b/arch/riscv/include/asm/asm-prototypes.h
@@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u);
DECLARE_DO_ERROR_INFO(do_trap_ecall_s);
DECLARE_DO_ERROR_INFO(do_trap_ecall_m);
DECLARE_DO_ERROR_INFO(do_trap_break);
+DECLARE_DO_ERROR_INFO(do_trap_software_check);
asmlinkage void handle_bad_stack(struct pt_regs *regs);
asmlinkage void do_page_fault(struct pt_regs *regs);
diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
index b28ccc6cdeea..34ed149af5d1 100644
--- a/arch/riscv/include/asm/entry-common.h
+++ b/arch/riscv/include/asm/entry-common.h
@@ -40,4 +40,6 @@ static inline int handle_misaligned_store(struct pt_regs *regs)
}
#endif
+bool handle_user_cfi_violation(struct pt_regs *regs);
+
#endif /* _ASM_RISCV_ENTRY_COMMON_H */
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 00494b54ff4a..9c00cac3f6f2 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -472,6 +472,9 @@ SYM_DATA_START_LOCAL(excp_vect_table)
RISCV_PTR do_page_fault /* load page fault */
RISCV_PTR do_trap_unknown
RISCV_PTR do_page_fault /* store page fault */
+ RISCV_PTR do_trap_unknown /* cause=16 */
+ RISCV_PTR do_trap_unknown /* cause=17 */
+ RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */
SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end)
#ifndef CONFIG_MMU
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 8ff8e8b36524..3f7709f4595a 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -354,6 +354,49 @@ void do_trap_ecall_u(struct pt_regs *regs)
}
+#define CFI_TVAL_FCFI_CODE 2
+#define CFI_TVAL_BCFI_CODE 3
+/* handle cfi violations */
+bool handle_user_cfi_violation(struct pt_regs *regs)
+{
+ bool ret = false;
+ unsigned long tval = csr_read(CSR_TVAL);
+
+ if ((tval == CFI_TVAL_FCFI_CODE && cpu_supports_indirect_br_lp_instr()) ||
+ (tval == CFI_TVAL_BCFI_CODE && cpu_supports_shadow_stack())) {
+ do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc,
+ "Oops - control flow violation");
+ ret = true;
+ }
+
+ return ret;
+}
+
+/*
+ * software check exception is defined with risc-v cfi spec. Software check
+ * exception is raised when:-
+ * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad`
+ * instruction or `label` value programmed in `lpad` instr doesn't
+ * match with value setup in `x7`. reported code in `xtval` is 2.
+ * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp)
+ * and x1/x5. reported code in `xtval` is 3.
+ */
+asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs)
+{
+ if (user_mode(regs)) {
+ irqentry_enter_from_user_mode(regs);
+
+ /* not a cfi violation, then merge into flow of unknown trap handler */
+ if (!handle_user_cfi_violation(regs))
+ do_trap_unknown(regs);
+
+ irqentry_exit_to_user_mode(regs);
+ } else {
+ /* sw check exception coming from kernel is a bug in kernel */
+ die(regs, "Kernel BUG");
+ }
+}
+
#ifdef CONFIG_MMU
asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs)
{
--
2.34.1
next prev parent reply other threads:[~2025-02-10 20:27 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-10 20:26 [PATCH v10 00/27] riscv control-flow integrity for usermode Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 01/27] mm: VM_SHADOW_STACK definition for riscv Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 02/27] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 03/27] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 05/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 06/27] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 07/27] riscv mm: manufacture shadow stack pte Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 08/27] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 09/27] riscv mmu: write protect and shadow stack Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 10/27] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 11/27] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 12/27] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 13/27] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2025-02-10 20:26 ` Deepak Gupta [this message]
2025-02-10 20:26 ` [PATCH v10 15/27] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 16/27] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 17/27] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 18/27] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 19/27] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 20/27] riscv: Add Firmware Feature SBI extensions definitions Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 21/27] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 22/27] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 23/27] arch/riscv: compile vdso with landing pad Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 24/27] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 25/27] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2025-02-10 20:26 ` [PATCH v10 26/27] riscv: Documentation for shadow stack on riscv Deepak Gupta
2025-02-10 20:27 ` [PATCH v10 27/27] kselftest/riscv: kselftest for user mode cfi Deepak Gupta
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