From: Peter Zijlstra <peterz@infradead.org>
To: Rik van Riel <riel@surriel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org, bp@alien8.de,
dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com,
nadav.amit@gmail.com, thomas.lendacky@amd.com,
kernel-team@meta.com, linux-mm@kvack.org,
akpm@linux-foundation.org, jannh@google.com,
mhklinux@outlook.com, andrew.cooper3@citrix.com,
Dave Hansen <dave.hansen@intel.com>
Subject: Re: [PATCH v8 03/12] x86/mm: consolidate full flush threshold decision
Date: Wed, 5 Feb 2025 13:20:07 +0100 [thread overview]
Message-ID: <20250205122007.GH14028@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20250205014033.3626204-4-riel@surriel.com>
On Tue, Feb 04, 2025 at 08:39:52PM -0500, Rik van Riel wrote:
> diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> index 6cf881a942bb..02e1f5c5bca3 100644
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c
> @@ -1000,8 +1000,13 @@ static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
> BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
> #endif
>
> - info->start = start;
> - info->end = end;
> + /*
> + * Round the start and end addresses to the page size specified
> + * by the stride shift. This ensures partial pages at the end of
> + * a range get fully invalidated.
> + */
> + info->start = round_down(start, 1 << stride_shift);
> + info->end = round_up(end, 1 << stride_shift);
> info->mm = mm;
> info->stride_shift = stride_shift;
> info->freed_tables = freed_tables;
Rather than doing this; should we not fix whatever dodgy users are
feeding us non-page-aligned addresses for invalidation?
next prev parent reply other threads:[~2025-02-05 12:20 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 1:39 [PATCH v8 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-02-05 1:39 ` [PATCH v8 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-02-05 1:39 ` [PATCH v8 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-02-05 1:39 ` [PATCH v8 03/12] x86/mm: consolidate full flush threshold decision Rik van Riel
2025-02-05 12:20 ` Peter Zijlstra [this message]
2025-02-05 13:00 ` Peter Zijlstra
2025-02-05 13:52 ` Rik van Riel
2025-02-05 1:39 ` [PATCH v8 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-02-05 1:39 ` [PATCH v8 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-02-05 1:39 ` [PATCH v8 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-02-05 1:39 ` [PATCH v8 07/12] x86/mm: use INVLPGB in flush_tlb_all Rik van Riel
2025-02-05 1:39 ` [PATCH v8 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-02-05 1:39 ` [PATCH v8 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-02-05 1:39 ` [PATCH v8 10/12] x86/mm: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-02-05 13:51 ` Peter Zijlstra
2025-02-05 14:52 ` Rik van Riel
2025-02-05 1:40 ` [PATCH v8 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-02-05 1:40 ` [PATCH v8 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
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