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From: Rik van Riel <riel@surriel.com>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org,
	dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com,
	nadav.amit@gmail.com, thomas.lendacky@amd.com,
	kernel-team@meta.com, linux-mm@kvack.org,
	akpm@linux-foundation.org, jannh@google.com,
	mhklinux@outlook.com, andrew.cooper3@citrix.com,
	Rik van Riel <riel@surriel.com>,
	Dave Hansen <dave.hansen@intel.com>
Subject: [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision
Date: Wed, 15 Jan 2025 21:30:26 -0500	[thread overview]
Message-ID: <20250116023127.1531583-4-riel@surriel.com> (raw)
In-Reply-To: <20250116023127.1531583-1-riel@surriel.com>

Reduce code duplication by consolidating the decision point
for whether to do individual invalidations or a full flush
inside get_flush_tlb_info.

Signed-off-by: Rik van Riel <riel@surriel.com>
Suggested-by: Dave Hansen <dave.hansen@intel.com>
---
 arch/x86/mm/tlb.c | 43 ++++++++++++++++++++-----------------------
 1 file changed, 20 insertions(+), 23 deletions(-)

diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 6cf881a942bb..2f38cf95dee3 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -1009,6 +1009,15 @@ static struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
 	info->initiating_cpu	= smp_processor_id();
 	info->trim_cpumask	= 0;
 
+	/*
+	 * If the number of flushes is so large that a full flush
+	 * would be faster, do a full flush.
+	 */
+	if ((end - start) >> stride_shift > tlb_single_page_flush_ceiling) {
+		info->start = 0;
+		info->end = TLB_FLUSH_ALL;
+	}
+
 	return info;
 }
 
@@ -1026,17 +1035,8 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
 				bool freed_tables)
 {
 	struct flush_tlb_info *info;
+	int cpu = get_cpu();
 	u64 new_tlb_gen;
-	int cpu;
-
-	cpu = get_cpu();
-
-	/* Should we flush just the requested range? */
-	if ((end == TLB_FLUSH_ALL) ||
-	    ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
-		start = 0;
-		end = TLB_FLUSH_ALL;
-	}
 
 	/* This is also a barrier that synchronizes with switch_mm(). */
 	new_tlb_gen = inc_mm_tlb_gen(mm);
@@ -1089,22 +1089,19 @@ static void do_kernel_range_flush(void *info)
 
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
 {
-	/* Balance as user space task's flush, a bit conservative */
-	if (end == TLB_FLUSH_ALL ||
-	    (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
-		on_each_cpu(do_flush_tlb_all, NULL, 1);
-	} else {
-		struct flush_tlb_info *info;
+	struct flush_tlb_info *info;
 
-		preempt_disable();
-		info = get_flush_tlb_info(NULL, start, end, 0, false,
-					  TLB_GENERATION_INVALID);
+	guard(preempt)();
+
+	info = get_flush_tlb_info(NULL, start, end, PAGE_SHIFT, false,
+				  TLB_GENERATION_INVALID);
 
+	if (end == TLB_FLUSH_ALL)
+		on_each_cpu(do_flush_tlb_all, NULL, 1);
+	else
 		on_each_cpu(do_kernel_range_flush, info, 1);
 
-		put_flush_tlb_info();
-		preempt_enable();
-	}
+	put_flush_tlb_info();
 }
 
 /*
@@ -1276,7 +1273,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
 
 	int cpu = get_cpu();
 
-	info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false,
+	info = get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, PAGE_SHIFT, false,
 				  TLB_GENERATION_INVALID);
 	/*
 	 * flush_tlb_multi() is not optimized for the common case in which only
-- 
2.47.1



  parent reply	other threads:[~2025-01-16  2:32 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-16  2:30 [PATCH v5 00/12] AMD broadcast TLB invalidation Rik van Riel
2025-01-16  2:30 ` [PATCH v5 01/12] x86/mm: make MMU_GATHER_RCU_TABLE_FREE unconditional Rik van Riel
2025-01-16  2:30 ` [PATCH v5 02/12] x86/mm: remove pv_ops.mmu.tlb_remove_table call Rik van Riel
2025-01-16  2:30 ` Rik van Riel [this message]
2025-01-17 19:23   ` [PATCH v5 03/12] x86/mm: consolidate full flush threshold decision Michael Kelley
2025-01-17 19:32     ` Rik van Riel
2025-01-16  2:30 ` [PATCH v5 04/12] x86/mm: get INVLPGB count max from CPUID Rik van Riel
2025-01-16  2:30 ` [PATCH v5 05/12] x86/mm: add INVLPGB support code Rik van Riel
2025-01-16  2:30 ` [PATCH v5 06/12] x86/mm: use INVLPGB for kernel TLB flushes Rik van Riel
2025-01-16  2:30 ` [PATCH v5 07/12] x86/tlb: use INVLPGB in flush_tlb_all Rik van Riel
2025-01-16  2:30 ` [PATCH v5 08/12] x86/mm: use broadcast TLB flushing for page reclaim TLB flushing Rik van Riel
2025-01-16  2:30 ` [PATCH v5 09/12] x86/mm: enable broadcast TLB invalidation for multi-threaded processes Rik van Riel
2025-01-16  2:30 ` [PATCH v5 10/12] x86,tlb: do targeted broadcast flushing from tlbbatch code Rik van Riel
2025-01-20  9:56   ` Nadav Amit
2025-01-20 14:02     ` Rik van Riel
2025-01-20 14:14       ` Nadav Amit
2025-01-20 16:11         ` Rik van Riel
2025-01-20 17:09           ` Nadav Amit
2025-01-20 17:11             ` Rik van Riel
2025-01-20 17:50               ` Nadav Amit
2025-01-20 17:56                 ` Rik van Riel
2025-01-20 18:56                   ` Nadav Amit
2025-01-21  2:33                     ` Rik van Riel
2025-01-16  2:30 ` [PATCH v5 11/12] x86/mm: enable AMD translation cache extensions Rik van Riel
2025-01-16  2:30 ` [PATCH v5 12/12] x86/mm: only invalidate final translations with INVLPGB Rik van Riel
2025-01-16 18:14 ` [PATCH v5 00/12] AMD broadcast TLB invalidation Michael Kelley
2025-01-16 22:37   ` Peter Zijlstra
2025-01-17  0:00     ` Andrew Cooper
2025-01-21 10:45       ` Peter Zijlstra
2025-01-21 17:14   ` Dave Hansen
2025-01-21 21:24     ` Michael Kelley
2025-01-21 17:22   ` Jann Horn
2025-01-21 21:39     ` Michael Kelley
2025-01-21 21:56       ` Jann Horn

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