From: Celeste Liu <uwu@coelacanthus.name>
To: Oleg Nesterov <oleg@redhat.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <kees@kernel.org>, Shuah Khan <shuah@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: "Alexandre Ghiti" <alex@ghiti.fr>,
"Dmitry V. Levin" <ldv@strace.io>,
"Andrea Bolognani" <abologna@redhat.com>,
"Björn Töpel" <bjorn@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Ron Economos" <re@w6rz.net>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Quan Zhou" <zhouquan@iscas.ac.cn>,
"Felix Yan" <felixonmars@archlinux.org>,
"Ruizhe Pan" <c141028@gmail.com>, "Guo Ren" <guoren@kernel.org>,
"Yao Zi" <ziyao@disroot.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, linux-kselftest@vger.kernel.org,
"Celeste Liu" <uwu@coelacanthus.name>,
stable@vger.kernel.org, "Björn Töpel" <bjorn@rivosinc.com>
Subject: [PATCH v6 1/3] riscv/ptrace: add new regset to access original a0 register
Date: Wed, 15 Jan 2025 19:13:27 +0800 [thread overview]
Message-ID: <20250115-riscv-new-regset-v6-1-59bfddd33525@coelacanthus.name> (raw)
In-Reply-To: <20250115-riscv-new-regset-v6-0-59bfddd33525@coelacanthus.name>
The orig_a0 is missing in struct user_regs_struct of riscv, and there is
no way to add it without breaking UAPI. (See Link tag below)
Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to
access original a0 register from userspace via ptrace API.
Fixes: e2c0cdfba7f6 ("RISC-V: User-facing API")
Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/
Cc: stable@vger.kernel.org
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Signed-off-by: Celeste Liu <uwu@coelacanthus.name>
---
arch/riscv/kernel/ptrace.c | 32 ++++++++++++++++++++++++++++++++
include/uapi/linux/elf.h | 1 +
2 files changed, 33 insertions(+)
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index ea67e9fb7a583683b922fe2c017ea61f3bc848db..ef9ab74c8575a5c440155973b1c625c06a867c97 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -31,6 +31,7 @@ enum riscv_regset {
#ifdef CONFIG_RISCV_ISA_SUPM
REGSET_TAGGED_ADDR_CTRL,
#endif
+ REGSET_ORIG_A0,
};
static int riscv_gpr_get(struct task_struct *target,
@@ -184,6 +185,29 @@ static int tagged_addr_ctrl_set(struct task_struct *target,
}
#endif
+static int riscv_orig_a0_get(struct task_struct *target,
+ const struct user_regset *regset,
+ struct membuf to)
+{
+ return membuf_store(&to, task_pt_regs(target)->orig_a0);
+}
+
+static int riscv_orig_a0_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ unsigned long orig_a0 = task_pt_regs(target)->orig_a0;
+ int ret;
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &orig_a0, 0, -1);
+ if (ret)
+ return ret;
+
+ task_pt_regs(target)->orig_a0 = orig_a0;
+ return 0;
+}
+
static const struct user_regset riscv_user_regset[] = {
[REGSET_X] = {
.core_note_type = NT_PRSTATUS,
@@ -224,6 +248,14 @@ static const struct user_regset riscv_user_regset[] = {
.set = tagged_addr_ctrl_set,
},
#endif
+ [REGSET_ORIG_A0] = {
+ .core_note_type = NT_RISCV_ORIG_A0,
+ .n = 1,
+ .size = sizeof(elf_greg_t),
+ .align = sizeof(elf_greg_t),
+ .regset_get = riscv_orig_a0_get,
+ .set = riscv_orig_a0_set,
+ },
};
static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index b44069d29cecc0f9de90ee66bfffd2137f4275a8..390060229601631da2fb27030d9fa2142e676c14 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -452,6 +452,7 @@ typedef struct elf64_shdr {
#define NT_RISCV_CSR 0x900 /* RISC-V Control and Status Registers */
#define NT_RISCV_VECTOR 0x901 /* RISC-V vector registers */
#define NT_RISCV_TAGGED_ADDR_CTRL 0x902 /* RISC-V tagged address control (prctl()) */
+#define NT_RISCV_ORIG_A0 0x903 /* RISC-V original a0 register */
#define NT_LOONGARCH_CPUCFG 0xa00 /* LoongArch CPU config registers */
#define NT_LOONGARCH_CSR 0xa01 /* LoongArch control and status registers */
#define NT_LOONGARCH_LSX 0xa02 /* LoongArch Loongson SIMD Extension registers */
--
2.48.0
next prev parent reply other threads:[~2025-01-15 11:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-15 11:13 [PATCH v6 0/3] " Celeste Liu
2025-01-15 11:13 ` Celeste Liu [this message]
2025-01-15 21:33 ` [PATCH v6 1/3] " Charlie Jenkins
2025-01-15 11:13 ` [PATCH v6 2/3] tools: copy include/linux/stddef.h to tools/include Celeste Liu
2025-01-15 11:35 ` Andrew Jones
2025-01-15 21:34 ` Charlie Jenkins
2025-01-15 11:13 ` [PATCH v6 3/3] riscv: selftests: Add a ptrace test to verify a0 and orig_a0 access Celeste Liu
2025-01-15 11:37 ` Andrew Jones
2025-01-15 22:43 ` [PATCH v6 0/3] riscv/ptrace: add new regset to access original a0 register Charlie Jenkins
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250115-riscv-new-regset-v6-1-59bfddd33525@coelacanthus.name \
--to=uwu@coelacanthus.name \
--cc=abologna@redhat.com \
--cc=ajones@ventanamicro.com \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=bjorn@kernel.org \
--cc=bjorn@rivosinc.com \
--cc=c141028@gmail.com \
--cc=charlie@rivosinc.com \
--cc=ebiederm@xmission.com \
--cc=felixonmars@archlinux.org \
--cc=guoren@kernel.org \
--cc=kees@kernel.org \
--cc=ldv@strace.io \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=linux-mm@kvack.org \
--cc=linux-riscv@lists.infradead.org \
--cc=oleg@redhat.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=re@w6rz.net \
--cc=shuah@kernel.org \
--cc=stable@vger.kernel.org \
--cc=tglx@linutronix.de \
--cc=zhouquan@iscas.ac.cn \
--cc=ziyao@disroot.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox