From: Celeste Liu <uwu@coelacanthus.name>
To: Oleg Nesterov <oleg@redhat.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Eric Biederman <ebiederm@xmission.com>,
Kees Cook <kees@kernel.org>, Shuah Khan <shuah@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: "Alexandre Ghiti" <alex@ghiti.fr>,
"Dmitry V. Levin" <ldv@strace.io>,
"Andrea Bolognani" <abologna@redhat.com>,
"Björn Töpel" <bjorn@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Ron Economos" <re@w6rz.net>,
"Charlie Jenkins" <charlie@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Quan Zhou" <zhouquan@iscas.ac.cn>,
"Felix Yan" <felixonmars@archlinux.org>,
"Ruizhe Pan" <c141028@gmail.com>, "Guo Ren" <guoren@kernel.org>,
"Yao Zi" <ziyao@disroot.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-mm@kvack.org, linux-kselftest@vger.kernel.org,
"Celeste Liu" <uwu@coelacanthus.name>,
stable@vger.kernel.org, "Björn Töpel" <bjorn@rivosinc.com>
Subject: [PATCH v6 0/3] riscv/ptrace: add new regset to access original a0 register
Date: Wed, 15 Jan 2025 19:13:26 +0800 [thread overview]
Message-ID: <20250115-riscv-new-regset-v6-0-59bfddd33525@coelacanthus.name> (raw)
The orig_a0 is missing in struct user_regs_struct of riscv, and there is
no way to add it without breaking UAPI. (See Link tag below)
Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to
access original a0 register from userspace via ptrace API.
Link: https://lore.kernel.org/all/59505464-c84a-403d-972f-d4b2055eeaac@gmail.com/
Signed-off-by: Celeste Liu <uwu@coelacanthus.name>
---
Changes in v6:
- Fix obsolute comment.
- Copy include/linux/stddef.h to tools/include to use offsetofend in
selftests.
- Link to v5: https://lore.kernel.org/r/20250115-riscv-new-regset-v5-0-d0e6ec031a23@coelacanthus.name
Changes in v5:
- Fix wrong usage in selftests.
- Link to v4: https://lore.kernel.org/r/20241226-riscv-new-regset-v4-0-4496a29d0436@coelacanthus.name
Changes in v4:
- Fix a copy paste error in selftest. (Forget to commit...)
- Link to v3: https://lore.kernel.org/r/20241226-riscv-new-regset-v3-0-f5b96465826b@coelacanthus.name
Changes in v3:
- Use return 0 directly for readability.
- Fix test for modify a0.
- Add Fixes: tag
- Remove useless Cc: stable.
- Selftest will check both a0 and orig_a0, but depends on the
correctness of PTRACE_GET_SYSCALL_INFO.
- Link to v2: https://lore.kernel.org/r/20241203-riscv-new-regset-v2-0-d37da8c0cba6@coelacanthus.name
Changes in v2:
- Fix integer width.
- Add selftest.
- Link to v1: https://lore.kernel.org/r/20241201-riscv-new-regset-v1-1-c83c58abcc7b@coelacanthus.name
---
Celeste Liu (3):
riscv/ptrace: add new regset to access original a0 register
tools: copy include/linux/stddef.h to tools/include
riscv: selftests: Add a ptrace test to verify a0 and orig_a0 access
arch/riscv/kernel/ptrace.c | 32 +++++
include/uapi/linux/elf.h | 1 +
tools/include/linux/stddef.h | 85 ++++++++++++
tools/include/uapi/linux/stddef.h | 6 +-
tools/testing/selftests/riscv/abi/.gitignore | 1 +
tools/testing/selftests/riscv/abi/Makefile | 6 +-
tools/testing/selftests/riscv/abi/ptrace.c | 193 +++++++++++++++++++++++++++
7 files changed, 319 insertions(+), 5 deletions(-)
---
base-commit: 0e287d31b62bb53ad81d5e59778384a40f8b6f56
change-id: 20241201-riscv-new-regset-d529b952ad0d
Best regards,
--
Celeste Liu <uwu@coelacanthus.name>
next reply other threads:[~2025-01-15 11:14 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-15 11:13 Celeste Liu [this message]
2025-01-15 11:13 ` [PATCH v6 1/3] " Celeste Liu
2025-01-15 21:33 ` Charlie Jenkins
2025-01-15 11:13 ` [PATCH v6 2/3] tools: copy include/linux/stddef.h to tools/include Celeste Liu
2025-01-15 11:35 ` Andrew Jones
2025-01-15 21:34 ` Charlie Jenkins
2025-01-15 11:13 ` [PATCH v6 3/3] riscv: selftests: Add a ptrace test to verify a0 and orig_a0 access Celeste Liu
2025-01-15 11:37 ` Andrew Jones
2025-01-15 22:43 ` [PATCH v6 0/3] riscv/ptrace: add new regset to access original a0 register Charlie Jenkins
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