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From: Deepak Gupta <debug@rivosinc.com>
To: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,  Borislav Petkov <bp@alien8.de>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	 x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	 Andrew Morton <akpm@linux-foundation.org>,
	 "Liam R. Howlett" <Liam.Howlett@oracle.com>,
	 Vlastimil Babka <vbabka@suse.cz>,
	 Lorenzo Stoakes <lorenzo.stoakes@oracle.com>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Arnd Bergmann <arnd@arndb.de>,
	 Christian Brauner <brauner@kernel.org>,
	 Peter Zijlstra <peterz@infradead.org>,
	Oleg Nesterov <oleg@redhat.com>,
	 Eric Biederman <ebiederm@xmission.com>,
	Kees Cook <kees@kernel.org>,  Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <shuah@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org,
	 linux-mm@kvack.org, linux-riscv@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-arch@vger.kernel.org,
	 linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
	 alistair.francis@wdc.com, richard.henderson@linaro.org,
	jim.shu@sifive.com,  andybnac@gmail.com, kito.cheng@sifive.com,
	charlie@rivosinc.com,  atishp@rivosinc.com, evan@rivosinc.com,
	cleger@rivosinc.com,  alexghiti@rivosinc.com,
	samitolvanen@google.com, broonie@kernel.org,
	 rick.p.edgecombe@intel.com, Deepak Gupta <debug@rivosinc.com>
Subject: [PATCH v8 17/29] riscv/traps: Introduce software check exception
Date: Mon, 11 Nov 2024 12:54:02 -0800	[thread overview]
Message-ID: <20241111-v5_user_cfi_series-v8-17-dce14aa30207@rivosinc.com> (raw)
In-Reply-To: <20241111-v5_user_cfi_series-v8-0-dce14aa30207@rivosinc.com>

zicfiss / zicfilp introduces a new exception to priv isa `software check
exception` with cause code = 18. This patch implements software check
exception.

Additionally it implements a cfi violation handler which checks for code
in xtval. If xtval=2, it means that sw check exception happened because of
an indirect branch not landing on 4 byte aligned PC or not landing on
`lpad` instruction or label value embedded in `lpad` not matching label
value setup in `x7`. If xtval=3, it means that sw check exception happened
because of mismatch between link register (x1 or x5) and top of shadow
stack (on execution of `sspopchk`).

In case of cfi violation, SIGSEGV is raised with code=SEGV_CPERR.
SEGV_CPERR was introduced by x86 shadow stack patches.

Signed-off-by: Deepak Gupta <debug@rivosinc.com>
---
 arch/riscv/include/asm/asm-prototypes.h |  1 +
 arch/riscv/include/asm/entry-common.h   |  2 ++
 arch/riscv/kernel/entry.S               |  3 +++
 arch/riscv/kernel/traps.c               | 42 +++++++++++++++++++++++++++++++++
 4 files changed, 48 insertions(+)

diff --git a/arch/riscv/include/asm/asm-prototypes.h b/arch/riscv/include/asm/asm-prototypes.h
index cd627ec289f1..5a27cefd7805 100644
--- a/arch/riscv/include/asm/asm-prototypes.h
+++ b/arch/riscv/include/asm/asm-prototypes.h
@@ -51,6 +51,7 @@ DECLARE_DO_ERROR_INFO(do_trap_ecall_u);
 DECLARE_DO_ERROR_INFO(do_trap_ecall_s);
 DECLARE_DO_ERROR_INFO(do_trap_ecall_m);
 DECLARE_DO_ERROR_INFO(do_trap_break);
+DECLARE_DO_ERROR_INFO(do_trap_software_check);
 
 asmlinkage void handle_bad_stack(struct pt_regs *regs);
 asmlinkage void do_page_fault(struct pt_regs *regs);
diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h
index 7b32d2b08bb6..0f6448583a87 100644
--- a/arch/riscv/include/asm/entry-common.h
+++ b/arch/riscv/include/asm/entry-common.h
@@ -28,4 +28,6 @@ void handle_break(struct pt_regs *regs);
 int handle_misaligned_load(struct pt_regs *regs);
 int handle_misaligned_store(struct pt_regs *regs);
 
+bool handle_user_cfi_violation(struct pt_regs *regs);
+
 #endif /* _ASM_RISCV_ENTRY_COMMON_H */
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index a1f258fd7bbc..aaef4604d841 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -471,6 +471,9 @@ SYM_DATA_START_LOCAL(excp_vect_table)
 	RISCV_PTR do_page_fault   /* load page fault */
 	RISCV_PTR do_trap_unknown
 	RISCV_PTR do_page_fault   /* store page fault */
+	RISCV_PTR do_trap_unknown /* cause=16 */
+	RISCV_PTR do_trap_unknown /* cause=17 */
+	RISCV_PTR do_trap_software_check /* cause=18 is sw check exception */
 SYM_DATA_END_LABEL(excp_vect_table, SYM_L_LOCAL, excp_vect_table_end)
 
 #ifndef CONFIG_MMU
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index 51ebfd23e007..225b1d198ab6 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -354,6 +354,48 @@ void do_trap_ecall_u(struct pt_regs *regs)
 
 }
 
+#define CFI_TVAL_FCFI_CODE	2
+#define CFI_TVAL_BCFI_CODE	3
+/* handle cfi violations */
+bool handle_user_cfi_violation(struct pt_regs *regs)
+{
+	bool ret = false;
+	unsigned long tval = csr_read(CSR_TVAL);
+
+	if (((tval == CFI_TVAL_FCFI_CODE) && cpu_supports_indirect_br_lp_instr()) ||
+		((tval == CFI_TVAL_BCFI_CODE) && cpu_supports_shadow_stack())) {
+		do_trap_error(regs, SIGSEGV, SEGV_CPERR, regs->epc,
+					  "Oops - control flow violation");
+		ret = true;
+	}
+
+	return ret;
+}
+/*
+ * software check exception is defined with risc-v cfi spec. Software check
+ * exception is raised when:-
+ * a) An indirect branch doesn't land on 4 byte aligned PC or `lpad`
+ *    instruction or `label` value programmed in `lpad` instr doesn't
+ *    match with value setup in `x7`. reported code in `xtval` is 2.
+ * b) `sspopchk` instruction finds a mismatch between top of shadow stack (ssp)
+ *    and x1/x5. reported code in `xtval` is 3.
+ */
+asmlinkage __visible __trap_section void do_trap_software_check(struct pt_regs *regs)
+{
+	if (user_mode(regs)) {
+		irqentry_enter_from_user_mode(regs);
+
+		/* not a cfi violation, then merge into flow of unknown trap handler */
+		if (!handle_user_cfi_violation(regs))
+			do_trap_unknown(regs);
+
+		irqentry_exit_to_user_mode(regs);
+	} else {
+		/* sw check exception coming from kernel is a bug in kernel */
+		die(regs, "Kernel BUG");
+	}
+}
+
 #ifdef CONFIG_MMU
 asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs)
 {

-- 
2.45.0



  parent reply	other threads:[~2024-11-11 20:54 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-11 20:53 [PATCH v8 00/29] riscv control-flow integrity for usermode Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 01/29] mm: Introduce ARCH_HAS_USER_SHADOW_STACK Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 02/29] mm: helper `is_shadow_stack_vma` to check shadow stack vma Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 03/29] dt-bindings: riscv: zicfilp and zicfiss in dt-bindings (extensions.yaml) Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 04/29] riscv: zicfiss / zicfilp enumeration Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 05/29] riscv: zicfiss / zicfilp extension csr and bit definitions Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 06/29] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 07/29] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 08/29] riscv mm: manufacture shadow stack pte Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 09/29] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 10/29] riscv mmu: write protect and shadow stack Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 11/29] riscv/mm: Implement map_shadow_stack() syscall Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 12/29] riscv/shstk: If needed allocate a new shadow stack on clone Deepak Gupta
2024-11-12  9:47   ` kernel test robot
2024-11-11 20:53 ` [PATCH v8 13/29] prctl: arch-agnostic prctl for shadow stack Deepak Gupta
2024-11-11 20:53 ` [PATCH v8 14/29] prctl: arch-agnostic prctl for indirect branch tracking Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 15/29] riscv: Implements arch agnostic shadow stack prctls Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 16/29] riscv: Implements arch agnostic indirect branch tracking prctls Deepak Gupta
2024-11-11 20:54 ` Deepak Gupta [this message]
2024-11-11 20:54 ` [PATCH v8 18/29] riscv: signal: abstract header saving for setup_sigcontext Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 19/29] riscv/signal: save and restore of shadow stack for signal Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 20/29] riscv/kernel: update __show_regs to print shadow stack register Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 21/29] riscv/ptrace: riscv cfi status and state via ptrace and in core files Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 22/29] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 23/29] riscv: Add Firmware Feature SBI extensions definitions Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 24/29] riscv: enable kernel access to shadow stack memory via FWFT sbi call Deepak Gupta
2024-11-13  3:15   ` kernel test robot
2024-11-13 16:13   ` Nick Hu
2024-11-14  1:06     ` Deepak Gupta
2024-11-14  1:20       ` Nick Hu
2024-11-14  1:25         ` Deepak Gupta
2024-11-14  6:17           ` Nick Hu
2024-11-14 15:50             ` Deepak Gupta
2024-11-15  3:19               ` Nick Hu
2024-11-11 20:54 ` [PATCH v8 25/29] riscv: kernel command line option to opt out of user cfi Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 26/29] riscv: create a config for shadow stack and landing pad instr support Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 27/29] riscv: Documentation for landing pad / indirect branch tracking Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 28/29] riscv: Documentation for shadow stack on riscv Deepak Gupta
2024-11-11 20:54 ` [PATCH v8 29/29] kselftest/riscv: kselftest for user mode cfi Deepak Gupta

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