From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Jonathan Corbet <corbet@lwn.net>,
Andrew Morton <akpm@linux-foundation.org>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Arnd Bergmann <arnd@arndb.de>, Oleg Nesterov <oleg@redhat.com>,
Eric Biederman <ebiederm@xmission.com>,
Shuah Khan <shuah@kernel.org>,
"Rick P. Edgecombe" <rick.p.edgecombe@intel.com>,
Deepak Gupta <debug@rivosinc.com>,
Ard Biesheuvel <ardb@kernel.org>,
Szabolcs Nagy <Szabolcs.Nagy@arm.com>,
Kees Cook <kees@kernel.org>
Cc: "H.J. Lu" <hjl.tools@gmail.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Florian Weimer <fweimer@redhat.com>,
Christian Brauner <brauner@kernel.org>,
Thiago Jung Bauermann <thiago.bauermann@linaro.org>,
Ross Burton <ross.burton@arm.com>,
David Spickett <david.spickett@arm.com>,
Yury Khrustalev <yury.khrustalev@arm.com>,
Wilco Dijkstra <wilco.dijkstra@arm.com>,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
kvmarm@lists.linux.dev, linux-fsdevel@vger.kernel.org,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, Mark Brown <broonie@kernel.org>
Subject: [PATCH v13 16/40] KVM: arm64: Manage GCS access and registers for guests
Date: Tue, 01 Oct 2024 23:58:55 +0100 [thread overview]
Message-ID: <20241001-arm64-gcs-v13-16-222b78d87eee@kernel.org> (raw)
In-Reply-To: <20241001-arm64-gcs-v13-0-222b78d87eee@kernel.org>
GCS introduces a number of system registers for EL1 and EL0, on systems
with GCS we need to context switch them and expose them to VMMs to allow
guests to use GCS.
In order to allow guests to use GCS we also need to configure
HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and
CHKFEAT will report GCS as disabled. Also enable fine grained traps for
access to the GCS registers by guests which do not have the feature
enabled.
In order to allow userspace to control availability of the feature to
guests we enable writability for only ID_AA64PFR1_EL1.GCS, this is a
deliberately conservative choice to avoid errors due to oversights.
Further fields should be made writable in future.
Reviewed-by: Thiago Jung Bauermann <thiago.bauermann@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/kvm_host.h | 12 ++++++++++++
arch/arm64/include/asm/vncr_mapping.h | 2 ++
arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++++++
arch/arm64/kvm/sys_regs.c | 27 +++++++++++++++++++++++++-
4 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 329619c6fa96..31887d3f3de1 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -448,6 +448,10 @@ enum vcpu_sysreg {
POR_EL0, /* Permission Overlay Register 0 (EL0) */
+ /* Guarded Control Stack registers */
+ GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */
+ GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */
+
/* FP/SIMD/SVE */
SVCR,
FPMR,
@@ -525,6 +529,10 @@ enum vcpu_sysreg {
VNCR(POR_EL1), /* Permission Overlay Register 1 (EL1) */
+ /* Guarded Control Stack registers */
+ VNCR(GCSPR_EL1), /* Guarded Control Stack Pointer (EL1) */
+ VNCR(GCSCR_EL1), /* Guarded Control Stack Control (EL1) */
+
VNCR(HFGRTR_EL2),
VNCR(HFGWTR_EL2),
VNCR(HFGITR_EL2),
@@ -1495,4 +1503,8 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val);
(system_supports_fpmr() && \
kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
+#define kvm_has_gcs(k) \
+ (system_supports_gcs() && \
+ kvm_has_feat((k), ID_AA64PFR1_EL1, GCS, IMP))
+
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm/vncr_mapping.h
index 06f8ec0906a6..e289064148b3 100644
--- a/arch/arm64/include/asm/vncr_mapping.h
+++ b/arch/arm64/include/asm/vncr_mapping.h
@@ -89,6 +89,8 @@
#define VNCR_PMSIRR_EL1 0x840
#define VNCR_PMSLATFR_EL1 0x848
#define VNCR_TRFCR_EL1 0x880
+#define VNCR_GCSPR_EL1 0x8C0
+#define VNCR_GCSCR_EL1 0x8D0
#define VNCR_MPAM1_EL1 0x900
#define VNCR_MPAMHCR_EL2 0x930
#define VNCR_MPAMVPMV_EL2 0x938
diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
index 1579a3c08a36..70bd61430834 100644
--- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
+++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h
@@ -17,6 +17,7 @@
#include <asm/kvm_mmu.h>
static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt);
+static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt);
static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
{
@@ -31,6 +32,11 @@ static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
{
ctxt_sys_reg(ctxt, TPIDR_EL0) = read_sysreg(tpidr_el0);
ctxt_sys_reg(ctxt, TPIDRRO_EL0) = read_sysreg(tpidrro_el0);
+
+ if (ctxt_has_gcs(ctxt)) {
+ ctxt_sys_reg(ctxt, GCSPR_EL0) = read_sysreg_s(SYS_GCSPR_EL0);
+ ctxt_sys_reg(ctxt, GCSCRE0_EL1) = read_sysreg_s(SYS_GCSCRE0_EL1);
+ }
}
static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt)
@@ -83,6 +89,17 @@ static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt)
return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64MMFR3_EL1, S1POE, IMP);
}
+static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt)
+{
+ struct kvm_vcpu *vcpu;
+
+ if (!cpus_have_final_cap(ARM64_HAS_GCS))
+ return false;
+
+ vcpu = ctxt_to_vcpu(ctxt);
+ return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR1_EL1, GCS, IMP);
+}
+
static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
{
ctxt_sys_reg(ctxt, SCTLR_EL1) = read_sysreg_el1(SYS_SCTLR);
@@ -96,6 +113,10 @@ static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
if (ctxt_has_s1pie(ctxt)) {
ctxt_sys_reg(ctxt, PIR_EL1) = read_sysreg_el1(SYS_PIR);
ctxt_sys_reg(ctxt, PIRE0_EL1) = read_sysreg_el1(SYS_PIRE0);
+ if (ctxt_has_gcs(ctxt)) {
+ ctxt_sys_reg(ctxt, GCSPR_EL1) = read_sysreg_el1(SYS_GCSPR);
+ ctxt_sys_reg(ctxt, GCSCR_EL1) = read_sysreg_el1(SYS_GCSCR);
+ }
}
if (ctxt_has_s1poe(ctxt))
@@ -150,6 +171,11 @@ static inline void __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
{
write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0);
write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0);
+ if (ctxt_has_gcs(ctxt)) {
+ write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0);
+ write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1),
+ SYS_GCSCRE0_EL1);
+ }
}
static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
@@ -181,6 +207,11 @@ static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
if (ctxt_has_s1pie(ctxt)) {
write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR);
write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0);
+
+ if (ctxt_has_gcs(ctxt)) {
+ write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR);
+ write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR);
+ }
}
if (ctxt_has_s1poe(ctxt))
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index dad88e31f953..bafdf6b31d25 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1641,6 +1641,15 @@ static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
return REG_RAZ;
}
+static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *r)
+{
+ if (kvm_has_gcs(vcpu->kvm))
+ return 0;
+
+ return REG_HIDDEN;
+}
+
/* cpufeature ID register access trap handlers */
static bool access_id_reg(struct kvm_vcpu *vcpu,
@@ -2376,7 +2385,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
ID_AA64PFR0_EL1_RAS |
ID_AA64PFR0_EL1_AdvSIMD |
ID_AA64PFR0_EL1_FP), },
- ID_SANITISED(ID_AA64PFR1_EL1),
+ ID_WRITABLE(ID_AA64PFR1_EL1, ID_AA64PFR1_EL1_GCS),
ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR),
ID_UNALLOCATED(4,3),
ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
@@ -2461,6 +2470,13 @@ static const struct sys_reg_desc sys_reg_descs[] = {
PTRAUTH_KEY(APDB),
PTRAUTH_KEY(APGA),
+ { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0,
+ .visibility = gcs_visibility },
+ { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1,
+ .visibility = gcs_visibility },
+ { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0,
+ .visibility = gcs_visibility },
+
{ SYS_DESC(SYS_SPSR_EL1), access_spsr},
{ SYS_DESC(SYS_ELR_EL1), access_elr},
@@ -2567,6 +2583,8 @@ static const struct sys_reg_desc sys_reg_descs[] = {
CTR_EL0_IDC_MASK |
CTR_EL0_DminLine_MASK |
CTR_EL0_IminLine_MASK),
+ { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0,
+ .visibility = gcs_visibility },
{ SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
{ SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
@@ -4661,6 +4679,9 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu)
if (kvm_has_fpmr(kvm))
vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM;
+
+ if (kvm_has_gcs(kvm))
+ vcpu->arch.hcrx_el2 |= HCRX_EL2_GCSEn;
}
if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags))
@@ -4714,6 +4735,10 @@ void kvm_calculate_traps(struct kvm_vcpu *vcpu)
kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
HFGxTR_EL2_nPOR_EL0);
+ if (!kvm_has_gcs(kvm))
+ kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nGCS_EL0 |
+ HFGxTR_EL2_nGCS_EL1);
+
if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP))
kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 |
HAFGRTR_EL2_RES1);
--
2.39.2
next prev parent reply other threads:[~2024-10-01 23:02 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 22:58 [PATCH v13 00/40] arm64/gcs: Provide support for GCS in userspace Mark Brown
2024-10-01 22:58 ` [PATCH v13 01/40] mm: Introduce ARCH_HAS_USER_SHADOW_STACK Mark Brown
2024-10-01 22:58 ` [PATCH v13 02/40] mm: Define VM_HIGH_ARCH_6 Mark Brown
2024-10-01 22:58 ` [PATCH v13 03/40] arm64/mm: Restructure arch_validate_flags() for extensibility Mark Brown
2024-10-01 22:58 ` [PATCH v13 04/40] prctl: arch-agnostic prctl for shadow stack Mark Brown
2024-10-01 23:13 ` Deepak Gupta
2024-10-01 22:58 ` [PATCH v13 05/40] mman: Add map_shadow_stack() flags Mark Brown
2024-10-01 22:58 ` [PATCH v13 06/40] arm64: Document boot requirements for Guarded Control Stacks Mark Brown
2024-10-01 22:58 ` [PATCH v13 07/40] arm64/gcs: Document the ABI " Mark Brown
2024-10-01 22:58 ` [PATCH v13 08/40] arm64/sysreg: Add definitions for architected GCS caps Mark Brown
2024-10-01 22:58 ` [PATCH v13 09/40] arm64/gcs: Add manual encodings of GCS instructions Mark Brown
2024-10-01 22:58 ` [PATCH v13 10/40] arm64/gcs: Provide put_user_gcs() Mark Brown
2024-10-01 22:58 ` [PATCH v13 11/40] arm64/gcs: Provide basic EL2 setup to allow GCS usage at EL0 and EL1 Mark Brown
2024-10-09 20:49 ` Nathan Chancellor
2024-10-10 15:18 ` Marc Zyngier
2024-10-10 17:16 ` Catalin Marinas
2024-10-11 12:55 ` Marc Zyngier
2024-10-14 16:31 ` Catalin Marinas
2024-10-15 13:05 ` Catalin Marinas
2024-10-01 22:58 ` [PATCH v13 12/40] arm64/cpufeature: Runtime detection of Guarded Control Stack (GCS) Mark Brown
2024-10-01 22:58 ` [PATCH v13 13/40] arm64/mm: Allocate PIE slots for EL0 guarded control stack Mark Brown
2024-10-01 22:58 ` [PATCH v13 14/40] mm: Define VM_SHADOW_STACK for arm64 when we support GCS Mark Brown
2024-10-01 22:58 ` [PATCH v13 15/40] arm64/mm: Map pages for guarded control stack Mark Brown
2024-10-01 22:58 ` Mark Brown [this message]
2024-10-02 0:24 ` [PATCH v13 16/40] KVM: arm64: Manage GCS access and registers for guests Marc Zyngier
2024-10-02 15:55 ` Marc Zyngier
2024-10-02 18:24 ` Mark Brown
2024-10-02 19:29 ` Marc Zyngier
2024-10-03 14:50 ` Mark Brown
2024-10-01 22:58 ` [PATCH v13 17/40] arm64/idreg: Add overrride for GCS Mark Brown
2024-10-01 22:58 ` [PATCH v13 18/40] arm64/hwcap: Add hwcap " Mark Brown
2024-10-03 16:25 ` Yury Khrustalev
2024-10-01 22:58 ` [PATCH v13 19/40] arm64/traps: Handle GCS exceptions Mark Brown
2024-10-01 22:58 ` [PATCH v13 20/40] arm64/mm: Handle GCS data aborts Mark Brown
2024-10-01 22:59 ` [PATCH v13 21/40] arm64/gcs: Context switch GCS state for EL0 Mark Brown
2024-10-01 22:59 ` [PATCH v13 22/40] arm64/gcs: Ensure that new threads have a GCS Mark Brown
2024-10-04 11:18 ` Catalin Marinas
2024-10-04 11:50 ` Mark Brown
2024-10-01 22:59 ` [PATCH v13 23/40] arm64/gcs: Implement shadow stack prctl() interface Mark Brown
2024-10-01 22:59 ` [PATCH v13 24/40] arm64/mm: Implement map_shadow_stack() Mark Brown
2024-10-01 22:59 ` [PATCH v13 25/40] arm64/signal: Set up and restore the GCS context for signal handlers Mark Brown
2024-10-01 22:59 ` [PATCH v13 26/40] arm64/signal: Expose GCS state in signal frames Mark Brown
2024-10-01 22:59 ` [PATCH v13 27/40] arm64/ptrace: Expose GCS via ptrace and core files Mark Brown
2024-10-01 22:59 ` [PATCH v13 28/40] arm64: Add Kconfig for Guarded Control Stack (GCS) Mark Brown
2024-10-01 22:59 ` [PATCH v13 29/40] kselftest/arm64: Verify the GCS hwcap Mark Brown
2024-10-01 22:59 ` [PATCH v13 30/40] kselftest/arm64: Add GCS as a detected feature in the signal tests Mark Brown
2024-10-01 22:59 ` [PATCH v13 31/40] kselftest/arm64: Add framework support for GCS to signal handling tests Mark Brown
2024-10-01 22:59 ` [PATCH v13 32/40] kselftest/arm64: Allow signals tests to specify an expected si_code Mark Brown
2024-10-01 22:59 ` [PATCH v13 33/40] kselftest/arm64: Always run signals tests with GCS enabled Mark Brown
2024-10-01 22:59 ` [PATCH v13 34/40] kselftest/arm64: Add very basic GCS test program Mark Brown
2024-10-01 22:59 ` [PATCH v13 35/40] kselftest/arm64: Add a GCS test program built with the system libc Mark Brown
2024-10-01 22:59 ` [PATCH v13 36/40] kselftest/arm64: Add test coverage for GCS mode locking Mark Brown
2024-10-01 22:59 ` [PATCH v13 37/40] kselftest/arm64: Add GCS signal tests Mark Brown
2024-10-01 22:59 ` [PATCH v13 38/40] kselftest/arm64: Add a GCS stress test Mark Brown
2024-10-01 22:59 ` [PATCH v13 39/40] kselftest/arm64: Enable GCS for the FP stress tests Mark Brown
2024-10-01 22:59 ` [PATCH v13 40/40] KVM: selftests: arm64: Add GCS registers to get-reg-list Mark Brown
2024-10-04 13:52 ` (subset) [PATCH v13 00/40] arm64/gcs: Provide support for GCS in userspace Catalin Marinas
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