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De Francesco 2021-04-23 941 * get_wave_count: Read device registers to get number of waves in flight for 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 942 * a particular queue. The method also returns the VMID associated with the 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 943 * queue. 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 944 * 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 945 * @adev: Handle of device whose registers are to be read 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 946 * @queue_idx: Index of queue in the queue-map bit-field 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 947 * @wave_cnt: Output parameter updated with number of waves in flight 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 948 * @vmid: Output parameter updated with VMID of queue whose wave count 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 949 * is being collected 3eeb0d037a5435 Srinivasan Shanmugam 2023-05-30 950 * @inst: xcc's instance number on a multi-XCC setup 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 951 */ 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 952 static void get_wave_count(struct amdgpu_device *adev, int queue_idx, 6ae9e1aba97e4c Mukul Joshi 2024-09-16 953 struct kfd_cu_occupancy *queue_cnt, uint32_t inst) 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 @954 { 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 955 int pipe_idx; 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 956 int queue_slot; 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 957 unsigned int reg_val; 6ae9e1aba97e4c Mukul Joshi 2024-09-16 958 unsigned int wave_cnt; 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 959 /* 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 960 * Program GRBM with appropriate MEID, PIPEID, QUEUEID and VMID 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 961 * parameters to read out waves in flight. Get VMID if there are 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 962 * non-zero waves in flight. 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 963 */ 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 964 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 965 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; e2069a7b0880cc Mukul Joshi 2022-05-09 966 soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, inst); 6ae9e1aba97e4c Mukul Joshi 2024-09-16 967 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, 6ae9e1aba97e4c Mukul Joshi 2024-09-16 968 mmSPI_CSQ_WF_ACTIVE_COUNT_0) + queue_slot); 6ae9e1aba97e4c Mukul Joshi 2024-09-16 969 wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; 6ae9e1aba97e4c Mukul Joshi 2024-09-16 970 if (wave_cnt != 0) { 6ae9e1aba97e4c Mukul Joshi 2024-09-16 971 queue_cnt->wave_cnt += wave_cnt; 6ae9e1aba97e4c Mukul Joshi 2024-09-16 972 queue_cnt->doorbell_off = 6ae9e1aba97e4c Mukul Joshi 2024-09-16 973 (RREG32_SOC15(GC, inst, mmCP_HQD_PQ_DOORBELL_CONTROL) & 6ae9e1aba97e4c Mukul Joshi 2024-09-16 974 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK) >> 6ae9e1aba97e4c Mukul Joshi 2024-09-16 975 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; 6ae9e1aba97e4c Mukul Joshi 2024-09-16 976 } 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 977 } 43a4bc828c5b15 Ramesh Errabolu 2020-09-29 978 :::::: The code at line 954 was first introduced by commit :::::: 43a4bc828c5b156f08024fd0a966c5c2a3f09af1 drm/amd/amdgpu: Define and implement a function that collects number of waves that are in flight. :::::: TO: Ramesh Errabolu :::::: CC: Alex Deucher -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki