[linux-next:master 13096/13213] drivers/irqchip/irq-riscv-imsic-early.c:52:47: error: too many arguments to function call, expected 2, have 3

[linux-next:master 13096/13213] drivers/irqchip/irq-riscv-imsic-early.c:52:47: error: too many arguments to function call, expected 2, have 3

[kernel test robot]

First bad commit (maybe != root cause):

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head:   82d92a9a1b9ea0ea52aff27cddd05009b4edad49
commit: f725fb3518e03b48a50a22f63c440cd04b41334a [13096/13213] Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
config: riscv-defconfig (https://download.01.org/0day-ci/archive/20240515/202405152211.4swEsJn5-lkp@intel.com/config)
compiler: clang version 19.0.0git (https://github.com/llvm/llvm-project d3455f4ddd16811401fa153298fadd2f59f6914e)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240515/202405152211.4swEsJn5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202405152211.4swEsJn5-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from drivers/irqchip/irq-riscv-imsic-early.c:9:
   In file included from include/linux/interrupt.h:21:
   In file included from arch/riscv/include/asm/sections.h:9:
   In file included from include/linux/mm.h:2253:
   include/linux/vmstat.h:514:36: warning: arithmetic between different enumeration types ('enum node_stat_item' and 'enum lru_list') [-Wenum-enum-conversion]
     514 |         return node_stat_name(NR_LRU_BASE + lru) + 3; // skip "nr_"
         |                               ~~~~~~~~~~~ ^ ~~~
>> drivers/irqchip/irq-riscv-imsic-early.c:52:47: error: too many arguments to function call, expected 2, have 3
      52 |         riscv_ipi_set_virq_range(virq, IMSIC_NR_IPI, true);
         |         ~~~~~~~~~~~~~~~~~~~~~~~~                     ^~~~
   arch/riscv/include/asm/smp.h:52:6: note: 'riscv_ipi_set_virq_range' declared here
      52 | void riscv_ipi_set_virq_range(int virq, int nr);
         |      ^                        ~~~~~~~~~~~~~~~~
   1 warning and 1 error generated.


vim +52 drivers/irqchip/irq-riscv-imsic-early.c

21a8f8a0eb35ce Anup Patel 2024-03-07  41  
21a8f8a0eb35ce Anup Patel 2024-03-07  42  static int __init imsic_ipi_domain_init(void)
21a8f8a0eb35ce Anup Patel 2024-03-07  43  {
21a8f8a0eb35ce Anup Patel 2024-03-07  44  	int virq;
21a8f8a0eb35ce Anup Patel 2024-03-07  45  
21a8f8a0eb35ce Anup Patel 2024-03-07  46  	/* Create IMSIC IPI multiplexing */
21a8f8a0eb35ce Anup Patel 2024-03-07  47  	virq = ipi_mux_create(IMSIC_NR_IPI, imsic_ipi_send);
21a8f8a0eb35ce Anup Patel 2024-03-07  48  	if (virq <= 0)
21a8f8a0eb35ce Anup Patel 2024-03-07  49  		return virq < 0 ? virq : -ENOMEM;
21a8f8a0eb35ce Anup Patel 2024-03-07  50  
21a8f8a0eb35ce Anup Patel 2024-03-07  51  	/* Set vIRQ range */
21a8f8a0eb35ce Anup Patel 2024-03-07 @52  	riscv_ipi_set_virq_range(virq, IMSIC_NR_IPI, true);
21a8f8a0eb35ce Anup Patel 2024-03-07  53  
21a8f8a0eb35ce Anup Patel 2024-03-07  54  	/* Announce that IMSIC is providing IPIs */
21a8f8a0eb35ce Anup Patel 2024-03-07  55  	pr_info("%pfwP: providing IPIs using interrupt %d\n", imsic->fwnode, IMSIC_IPI_ID);
21a8f8a0eb35ce Anup Patel 2024-03-07  56  
21a8f8a0eb35ce Anup Patel 2024-03-07  57  	return 0;
21a8f8a0eb35ce Anup Patel 2024-03-07  58  }
21a8f8a0eb35ce Anup Patel 2024-03-07  59  #else
21a8f8a0eb35ce Anup Patel 2024-03-07  60  static void imsic_ipi_starting_cpu(void) { }
21a8f8a0eb35ce Anup Patel 2024-03-07  61  static void imsic_ipi_dying_cpu(void) { }
21a8f8a0eb35ce Anup Patel 2024-03-07  62  static int __init imsic_ipi_domain_init(void) { return 0; }
21a8f8a0eb35ce Anup Patel 2024-03-07  63  #endif
21a8f8a0eb35ce Anup Patel 2024-03-07  64  

:::::: The code at line 52 was first introduced by commit
:::::: 21a8f8a0eb35ceb21e2c9ddd87468bc3b5ac87c0 irqchip: Add RISC-V incoming MSI controller early driver

:::::: TO: Anup Patel <apatel@ventanamicro.com>
:::::: CC: Thomas Gleixner <tglx@linutronix.de>

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